You may be wondering about D and A which I ignore. D controls interrupts from debugging features such as breakpoints and single stepping. A controls interrupts from "Serrors" which are asynchronous memory errors -- things I don't yet fully understand and which are probably only important in a sick system.
I manipulate these bits using inline assembly via the following macros:
#define INT_unlock asm volatile("msr DAIFClr, #3" : : : "cc")
#define INT_lock asm volatile("msr DAIFSet, #3" : : : "cc")
I use the "lock" macro to enter a critical section, then use
the "unlock" macro to exit from it.
In aarch32 these bits (or AIF at any rate) were located in the CPSR
register. On aarch64 the above instructions provide a much handier
way to manipulate them. On aarch64 what was the single CPSR register
is replaced by a "concept" called PSTATE which cannot be accessed by
a single instruction. What they say is that PSTATE is
"an abstraction of process state information".
I also have the following two macros. I only ever use the "get" macro. To change the bits I always use the lock/unlock macros above.
#define get_DAIF(val) asm volatile ( "mrs %0, DAIF" : "=r" ( val ) ) #define set_DAIF(val) asm volatile ( "msr DAIF, %0" : : "r" ( val ) )Note that the value returned (or set) by this routine is (or must be) left shifted 6 bits.
When packets are received, the receive ring is handled within interrupt code which runs with interrupts disabled without any special effort on my part.
Tom's electronics pages / tom@mmto.org