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Allwinner H5 network driver -- Cache questions

The D cache can be disabled by clearing the C bit (bit 2) in the System Control Register (SCTLR_ELx, where x=1, 2, or 3)

Before the disable, one should use DC CVAC (Clean by VA to PoC) or DC CIVAC (Clean & Invalidate) to flush dirty data to memory

The I cache can be disabled by clearing the I bit (bit 12) in the System Control Register (SCTLR_ELx)

Unlike the D cache, there exists a single instruction to invalidate the entire cache. This is IC IVAU, which should be followed by DSB and ISB.

Controlling the L2 cache can be a bit mysterious. Apparently on the A53, disabling the D cache by clearing the C bit also disables the L2 cache for that core.

There is a register L2CTLR_EL1 that is typically read only and can give information about L2 configuration.

There may be bits in the CPUACTLR_EL1 that control aspects of the L2 cache operation.

The MMU is controlled by bit 0 of the SCTLR

Check the cache bits when we boot Kyu

Kyu starting with SCTLR = 30c51835
D cache enabled
I cache enabled
MMU enabled
RAM 2048M total starting at 40000000

Also note the reported 2G of ram. This is an error. The Orange Pi PC2 has only 1G of ram, and it must be aliased a second time in the address space.

Take a look at U-boot

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