June 11, 2022

Fooling with the RISC-V

The RISC-V is a open CPU core that was designed at the University of California, Berkeley. The project began in 2010, and by 2019 reached a level of maturity that has attracted a number of companies into making hardware.

Note that there are many RISC-V variants. There is a 16 bit version, which may make a nice toy if you want to play with an FPGA. The usual hardware in production seems to be the 32 bit flavor. There is a 64 bit design, as well as a design with a 128 bit address space. This is university research after all.

The RISC-V is the darling of some components of the open source community. I find this a bit perplexing -- the typical "hacker" is not going to start producing parts in silicon, and while you could certainly put the design into an FPGA, I don't really see advantages to doing so. ARM processors are available and cheap. I don't mind if ARM makes some money licensing them.

The main appeal is for reasons of "PMS" (perceived moral superiority). There is no particular technical merit when compared to an ARM or Xtensa processor.

All this being said, there is absolutely nothing wrong with the RISC-V, at least not that I have discovered in my dealings with it thus far.

There is endless further confusion and mythology related to RISC versus CISC. Some imbeciles seem persuaded that a CISC design is somehow superior. The only CISC design I am aware of in current production is the x86. It only persists as what it is because it is shackled to certain software that people expect to run on it. RISC is superior in every merit that I am aware of, and I am certain that Intel could produce an even faster processor if they did not have to maintain software compatibility with certain products. It is impressive what Intel accomplishes within the limits of the absurd and outdated x86 instruction set.
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Tom's Computer Info / tom@mmto.org