January 9, 2023
Kyu networking -- PHY chips and their registers
My interest is in the Allwinner H3 chip, which as a built in 10/100 PHY.
The H3 datasheet however seems to say absolutely nothing about the onboard PHY!
My idea is that I can learn from other PHY chips and software.
The BBB (with the AM3358 chip from TI) has a perfectly good driver that is
working just fine with Kyu, so this could be a good starting point.
In this case, the PHY is an external chip, the SMSC (now Microchip) 8710A.
This is a nice high quality datasheet.
My interest at this point is in what registers a chip like this contains.
The MDIO spec says there can be up to 32 of them.
Chapter 4 describes the registers and claims that
"All registers follow the IEEE 802.3 clause 22.2.4 management register set.
I might be well served to find the IEEE 802.3 specification.
Clause 22 describes the MDIO interface (with later modifications by clause 45).
Clause 28 describes autonegotiation.
The 8710A datasheet calls this out as "IEEE 802.3-2005".
The registers in the 8710A chip are:
- 0 - basic control
- 1 - basic status
- 2 - PHY ID 1 -- 0x0007
- 3 - PHY ID 2 -- 0xC0Fx
- 4 - autonegotiation advertisement
- 5 - autonegotiation link partner ability
- 6 - autonegotiation expansion
- 17 - mode control/status
- 18 - special modes
- 26 - symbol error counter
- 27 - control/status indicator
- 29 - interrupt source
- 30 - interrupt mask
- 31 - PHY special control/status
Register 17-31 are marked as "vendor specific"
The Kyu driver for the BBB
- It initializes the MDIO by setting an enable bit and a divisor
- It has mdio read and write routines with various delays and such
- It uses PHY address 0 to talk to the 8710A
- It verifies the PHY by reading the two ID registers
- It does a PHY reset via the control register
- performing a reset apparently starts autonegotiation
- It watches the status register to know when autonegotiation finishes
- It matches bits in the advertisement and peer ability register to set speed and duplex
That is basically it. It initializes mdio and verifies the phy.
Then it resets the PHY and waits for autonegotiation to finish.
Then it determines the result (link status - which is speed and duplex).
The divisor it sets to initialize the mdio is 0xff (255)
This divides CLK (whatever it is) by div+1 (hence 256 in this case).
If CLK is the cpu clock (1000 Mhz) this would yield 3.9 Mhz.
One way to look at this is that it is generating the slowest possible clock
by using the maximum divisor. As long as this works (and apparently it does)
there is no harm done, the amount of traffic over the MDIO is miniscule.
Let's compare registers in the RTL8211E --
(Note the link to some TI PHY chips -- that I never did look at.)
Those marked with "*" are new (or different) for the RTL8211E.
- 0 - basic control
- 1 - basic status
- 2 - PHY ID 1 -- 0x001c
- 3 - PHY ID 2 -- 0xc915
- 4 - autonegotiation advertisement
- 5 - autonegotiation link partner ability
- 6 - autonegotiation expansion
- 7 * autonegotiation next page transmit
- 8 * autonegotiation next page receive
- 9 * 1000base-T control
- 10 * 1000base-T status
- 11 -- reserved
- 12 -- reserved
- 13 * MMD access control
- 14 * MMD access address data
- 15 * 1000base-T extended status
- 16 * PHY specific control
- 17 - PHY specific status
- 18 * interrupt enable
- 19 * interrupt status
- 24 * receive error counter
- 31 * page select
They certainly look the same through the first 6.
Given that the 8211 supports gigabit, it isn't surprising it has additional registers.
The 802.3-2005 document
This is huge. I am able to download it in sections (4 of them).
Section 2 has "Clause 22" which does discuss MII and does list registers.
Section 22.2.4 (on page 24) is entitled "management functions".
It says that all PHY that provide MII shall incorporate the basic set, which
consists of just the control and status (registers 0 and 1).
Registers 2-14 are called "extended".
What is not clear is how PHY addressing is handled.
I get the impression (probably wrong) that if there is only a single PHY present
(which is almost always the case, though there could be 32), it will respond on
address 0. The 8211 has 3 package pins to set the address.
Presumably in a single PHY system these would all be pulled to 0.
And we could of course only have 8 of the 8211 devices in a system,
which is a limitation that I doubt that many have ever complained about.
Similarly, the 8710A provides 3 package pins to set the address.
Have any comments? Questions?
Drop me a line!
Kyu / tom@mmto.org