The Xilinx Zynq 7010 FPGA resources

First of all, Zynq is a family with many members. Most of those are bigger, faster and more capable than what I am working with. What I have on my Antminer S9 and EBAZ boards is a xc7z010clg400-1 and that is what we will talk about here.

• Artix-7 FPGA architecture
• 28,000 logic cells
• 17,600 LUT
• 35,200 flip flops
• 2.1 Mb total block ram
• 60 blocks of block ram, each with 36kb
• 80 DSP slices

The Zynq I have has a CLB as the basic unit. Each CLB has two slices. Each slice has 4 LUT and 8 flip flops. Thus my Zynq has 2200 CLB and 4400 slices.

(Note: things are not quite this simple. There are two kinds of slices. There are SLICEM and SLICEL -- more on this below).

A CLB also includes two 4-bit cascadable adders.

A DSP slice has a 16x25 bit signed multiply along with a 48 bit adder/accumulator.

Block ram is true dual port memory. Each block is 36Kb, up to 36 bit wide. It can also be configured as dual 18Kb ram blocks.

Each LUT is a true 6 input LUT. It can be configured as a 6 input LUT with a 64 bit ROM or as two 5 input LUT with a 32 bit ROM. A slice has 8 flip flops to allow each 5 input LUT to feed a flip flop if it is configured that way.

Flip flops can also be configured as distributed 64 bit RAM cells or as 32 bit shift registers (or two 16 bit shift registers).

• BYU - Xilinx deep dive