Verilog or VHDL

There is no clear winner. Verilog seems most commonly used in the USA and VHDL elsewhere. This seems odd given that VHDL was designed in the USA by the DOD. People say you will end up using both. Vivado will accept either, along with "system verilog". I have read that the release of Verilog into the public domain was provoked by the advent of VHDL.

I was amused by the following advice. If you are in the USA, learn Verilog. If you get a defense related job, use the time waiting for your security clearance to learn VHDL.

VHDL is stricter, with a more rigorous and detailed type system. It is also less like C programming, which may be good for a habitual C programmer like myself -- it will remind me I am doing logic design not writing programs.