July 9, 2022

Verilog - Simulation versus Synthesis

I find it endlessly annoying that virtually all of the Verilog books and resources fail to make it clear that there are two ways to use the language.
The one exception to this is the book "The Verilog Hardware Description Language" by Thomas and Moorby.

What it boils down to is that a certain style must be used in writing Verilog that is intended for synthesis, and only a subset of the language can be synthesized.

Thomas and Moorby say that you should carefully study the synthesis manual for whatever software you are using. In my case that is Vivado and the manual is "ug901" (302 pages).

Synthesis refers to "compiling" the design into a form that can be loaded into an FPGA. There are many Verilog constructs that pertain only to simulation and which cannot be used in synthesis. Why don't books have a table or appendix that spells this out? Many books are written with simulation only in mind (since students in a classroom setting may deal only with simulation and have no access to FPGA hardware). Such books start to treat Verilog like yet another programming language and lure the student into thinking this way, which is at best misleading. I suppose the idea is that they will learn about synthesis on the job after they graduate.

I think the people writing many of the books have been teaching classes for so long that only ever use simulators that they have forgotten the real world of synthesis.

I am coming at this from an entirely different angle, wanting exclusively (and immediately) to be able to synthesis designs and run them on an FPGA. I understand the value of simulation and "testbench" code prior to synthesis.

Enough axe grinding. Here are some links that spell out (in part at least) which constructs are allowed in synthesis and which are not.

Here is my partial list of things that are not allowed in synthesis: A note on initial blocks. Depending on the device, you may be able to synthesize these, particularly for an FPGA. A general recommendation is to avoid this and to make such sections depend on a reset signal instead. This has several advantages, not the least of which being that you get predictable behavior on a reset.

What happens when you synthesize a "for" loop. This is not a programming language after all. What happens is that the loop gets "unrolled" -- in other words, hardware gets replicated to perform each "iteration" of the loop. The best way to think of the Verilog "for" statement is that it replicates the "loop body" not that it executes a loop. Maybe it would have been better to name it "replicate".

While loops cannot be synthesized, but can be useful in writing testbench code for simulation.

Feedback? Questions? Drop me a line!

Tom's Computer Info / tom@mmto.org