Vivado EMIO project using Tcl

I have s9_emio already that has 51 emio pins configured to go to the 47 externally routed FPGA signals and the 4 onboard LED. This time I am repeating that projet, but setting up the Tcl scripts so I can put it on Github, as well as use it as a jumping off port to add fancy LED control.

• This project on Github
• All of my Antminer S9 projects on Github

I start by making a throw-away block diagram project I call "zzz". I launch Vivado and use the create project "wizard".
The part is xc7z010clg400-1.

Next we create a block design. The usual "design_1" default will be fine. I add the Zynq block and do two customizations:

• Under PS-PL configuration we turn off the AXI GP0 interface (see AXI non-secure)
• Under MIO, under GPIO find EMIO and change width from 64 to 47.

Go to Sources, expand Design Sources, then select design_1 and get a menu. Select "create HDL wrapper".

The constraint file

We could have done this right up front, but it doesn't hurt at all to do it after setting up the model and generating the HDL wrapper.

Under "sources" I use the big "+" and change the selection to "add or create constraints". Then I used the "add" button, navigate to where my constraint file is, and add it.

Generate bitstream

/u1/home/tom/vivado/zzz/zzz.runs/impl_1/design_1_wrapper.bit

Test the bitstream

And we have a bitstream!

/u1/home/tom/vivado/s9_emio/s9_emio.runs/impl_1/design_1_wrapper.bit

Conclusion