December 3, 2024

Antminer S9 - Vivado and a new AXI peripheral - round 1

Several online tutorials give examples using the "Create and package new IP" tool in Vivado: Video 1 starts well, but he ends up creating a Stream master that just emits a clock.
Video 2 is an hour long, but seems very good.

Let's get started

To get started, the trick is to use "Tools" -- "Create and package new IP". This launches a new IP wizard.

The wizard is very simple. I choose AXI Lite and select (for no particular reason) 7 registers. The default is that they are 32 bits wide. When I get done I just save the IP in my own directory. This is also a default: 

/home/tom/vivado/ip_repo/s9_leds_1_1
/home/tom/vivado/ip_repo/s9_leds_1_1/hdl
The interesting thing is the pair of verilog files in the "hdl" directory: 
-rw-r--r-- 1 tom tom 15672 Dec  3 20:34 s9_leds_v1_0_S00_AXI.v
-rw-r--r-- 1 tom tom  2213 Dec  3 20:34 s9_leds_v1_0.v

Poking around in these, I find "slv_reg0" thru "slv_reg6" as names for the seven registers I asked for. Note that when reading these files, the comments refer to "reading the registers", this means the read is coming from the AXI bus (i.e. the PS). Writing is just the opposite, note that on reset all registers are "written" with zeros.

The next step will be learning how to edit these and also to add some verilog files of our own.

A new IP block

Even though we haven't done anything yet other than create a boilerplate template, this new block now exists when we use the big "+" button to add IP!! We can add it and then run connection automation!

However, I tried the experiment of starting a new project and seeing if the "+" button would find s9_leds and it failed, so something needs to be done to add the "ip_repo"

Here is what to do.

Indeed, this works and now I can add my new (but useless) block to the block model.

A significant puzzle for later will be learning how to discover the addresses to access the registers we have just created.

Note that at the top of the block diagram are tabs for "Address Editor" and "Address Map". These yield the desired information.

My block (nothing but the boilerplate) gets assigned a 64K block at 0x43C0_0000. In other words from 0x43c0_0000 to 0x43c0_ffff (all this for 7 registers). This can be found in both the "Address Editor" and "Address Map" tabs, It also appears in a line below in the "Tcl console" as: 
Slave segment '/s9_leds_0/S00_AXI/S00_AXI_reg' is being assigned into address space '/processing_system7_0/Data' at <0x43C0_0000 [ 64K ]>.

Try something simple

I edit the file s9_leds_v1_0_S00_AXI.v and change one line in the block that handles reset: 
slv_reg0 <= 32'hdeadabcd;
I create the HDL wrapper. I gives a bunch of warnings telling me to upgrade the IP for my gadget.
I do "run synthesis". I neglect to click anything in the popup telling me this is done and it launches right into the next thing, which I hope is "run implementation". Apparently it is, when it finishes I remember and change the radio button to "generate bitstream".
The bitstream is at: 
/u1/home/tom/vivado/s9_junk2/s9_junk2.runs/impl_1/design_1_wrapper.bit
I add some code to the Kyu Zynq port I am working on, copy the bitstream so it will get loaded, recompile and boot it up and I see: 
AXI reg 0 = deadabcd
Success! This wasn't a total nightmare like I thought it might have been. Another little experiment followed. I could write to register 0, which overwrote the reset value (as it should) and was then able to read back the value I had written. I tried the same thing for register 1, the only difference being tht the reset value there was zero, and of course that worked also.

It would easily be possible to modify the IP so that registers were read only and writes would be ignored. We could also have write only registers, but I hardly see any point in that.

IP block documentation

This is an out of context note, but it needs to go somewhere. When working with the supplied IP blocks, you can double click on the to customize them. In general this brings up some kind of dialog, and I have discovered that it seems to be a convention to put a button at the upper left to fetch documentation on the IP, for example: 
pg144-axi-gpio.pdf
pg082-processing-system7.pdf
Feedback? Questions? Drop me a line!

Tom's Computer Info / tom@mmto.org