I start a new project. I call it "first". It will be an RTL project. I select the Antminer S9 board, and finish.
Now I have the Vivado GUI in front of me. At the bottom is a selection of tabs from left to right. I select "TclConsole" on the left.
I poke around a bit in my home directory. I find that the file "vivado.log" has the information that is in the TclConsole along with lots of warnings and chatter that are not there.
The Tcl console shows me:
start_gui create_project first /u2/home/tom/vivado/first -part xc7z010clg400-1 INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/u1/Xilinx/Vivado/2024.2/data/ip'. set_property board_part cholla.mmto.org:s9:part0:1.0 [current_project]I select "create block design" under IP integrator. I give it the design name "emio".
create_bd_design "emio" Wrote : update_compile_order -fileset sources_1Now I use the "+" button to add IP and select "ZYNQ7 Processing System".
startgroup create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 endgroupNow, as suggested, I run block automation, taking the defaults:
apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0]
After this, I see it has hooked up DDR and FIXED_IO. Next I double click on the big ZYNQ block and get a big fancy diagram.
Ignore the diagram and select MIO configuration on the left. Open up IO Peripherals, select GPIO at the bottom and turn
on EMIO GPIO. I give it a width of 64. Once you click "OK", the block will show a new GPIO_0 output on the right side
above DDR. Yes, this is quite obscure and hidden. The resulting Tcl is simply:
startgroup
set_property CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} [get_bd_cells processing_system7_0]
endgroup
If you change your mind and want to turn this off again, use:
set_property CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} [get_bd_cells processing_system7_0]
I don't see the value 64 even mentioned in the resulting Tcl. I try changing it to other values,
and no new Tcl commands result. This is probably just a value that gets communicated to the SDK
so that C code can be properly generated. Now I right click on that new GPIO_O that has shown
up in the block diagram and select "make external". This gives me an "output arrow" on the
block diagram and some new Tcl results:
startgroup make_bd_intf_pins_external [get_bd_intf_pins processing_system7_0/GPIO_0] endgroupDon't ask me why everything get sandwiched inside startgroup/endgroup. Actually, you can look these up in UG835, the 2000 page Tcl command reference. All they do is to define sets of commands that can be unrolled by "undo" or repeated by "redo".
Now I go over to "PROJECT MANAGER" on the left and click "Add Sources". I select "Add or Create Constrains". I use the "+" and navigate to:
/home/tom/vivado/first/emio_all.xdcNote that I had already copied the constraint file to the location above so I would know where to find it. At the bottom of this window I enable the checkbox "copy constraint files into project" then click "finish". In the Tcl window I see:
add_files -fileset constrs_1 -norecurse /u2/home/tom/vivado/first/emio_all.xdc import_files -fileset constrs_1 /u2/home/tom/vivado/first/emio_all.xdcWhy do we both do the "add" and "import"? Reading the big Tcl document tells me that "add_files" adds sources to the active fileset. It says that "import_files" imports files and/or directories. It goes on the explain how this is different from add_files. It imports the files (which I guess means that it copies them), then it adds the to the active fileset. So it would seem that just "import_files" would do it all. Or maybe just "add_files" would work since I already put the file where I wanted it.
Tom's Computer Info / tom@mmto.org