January 22, 2025

Antminer S9 board - NAND hardware

My old U-boot tells me this about NAND on the S9 when it starts up. 
Xilinx First Stage Boot Loader
Release 2015.4	Mar 29 2018-17:25:31
.....
U-Boot 2014.01-gfb1d3e7-dirty (Mar 09 2018 - 19:36:04)
.....
---1 sys_sdram_size = 0x20000000
--- dram_init: sys_sdram_size = 512 MB

---3 gd->ram_size = 0x1f000000
Memory: ECC disabled
DRAM:  496 MiB
NAND:  256 MiB
MMC:   zynq_sdhci: 0
When I get to the U-boot prompts, I can type: 
zynq-uboot> nand info

Device 0: nand0, sector size 128 KiB
  Page size      2048 b
  OOB size         64 b
  Erase size   131072 b

The NAND chip on my board is made by Micron, a 29F2G08ABAEA. It is a 3.3 volt device with an 8 bit bus. It has what Micron calls an ONFI interface, which is "Open NAND flash interface".

The schematic shows a MT29F2G08AACWP. It is a 48 pin device, but it looks like about half the pins are no-connects.

We have an 8 bit bidirectional data bus and these signals: 

R/B*
ALE
CLE
WE*
WP*
RE*
CS*

This is handled by the MTD driver in U-boot (and linux). See drivers/mtd/nand/raw for U-boot.

There is interesting information in the U-Boot device tree files.
Look at arch/arm/dts/zynq-7000.dtsi 

smcc: memory-controller@e000e000 {
....
....
  nand0: flash@e1000000 {
                status = "disabled";
                compatible = "arm,pl353-nand-r2p1";
                reg = <0xe1000000 0x1000000>;
                #address-cells = <1>;
                #size-cells = <1>;
            };

What does the Zynq TRM say about all this?

This is section 11 of the TRM, entitled "Static Memory Controller". They say, "The SMC is based on ARM's PL353 static memory controller." It can handle NAND flash via the ONFI specification, or NOR flash via a parallel interface, but not both.

There is a separate SPI flash controller for that sort of flash, as well as an SD/SDIO controller for the flash card.

Registers are at 0xe000_e000 and there are three associated memory areas: 

0xe100_0000 - SMC NAND
0xe200_0000 - SMC SRAM 0
0xe400_0000 - SMC SRAM 1
Some registers are common to both, some are exclusive to NAND and some are exclusive to NOR.

You are refered to the "ARM Static Memory Controller (PL350 series) Technical Reference Manual". It is easily available online as a document from ARM and is 174 pages. This explains why the section in the TRM on this is only 10 pages. We have the PL353, which handles both SRAM and NAND. NAND has multiplexed address and data.

Pages 1710 through 1736 in the Zynq TRM describe the registers.

For a start, take a look at: 

drivers/mtd/nand/raw/zynq_nand.c
This is a 1200+ line file, and there are several other nand*.c files in the same directory that total to 9000+ lines, so there is a lot to digest.
Feedback? Questions? Drop me a line!

Tom's Computer Info / tom@mmto.org