December 12, 2024

Antminer S9 - Vivado and the S9 led project

The idea here is to combine two things I have been experimenting with and generate one bitstream that it suitable for general use.

The first thing is to connect EMIO to all of the on-board resources that I don't want to access in other ways. This is easy, now that I understand how to do it -- the bulk of the work will be in putting together a constraint file that has everything in it.

The second thing is a fancy interface to the four on-board LED. Some of this was done already (in Verilog) for an EBAZ project. For the EBAZ I used an AXI GPIO block. For this project I want to use a custom IP block that will have 8 registers.

Here is a simple example that I am trying to follow:

Get started

I launch Vivado (2022.2) and start up a new project I name "s9_led2". I use "Create Block Design" and pull in the Zynq processing system. As usual, I accept the default and call this "design_1". I double click the Zynq block to customize it.

Under PS/PL configuration, I go to AXI non-secure, find AXI GP0 interface and disable it. This turns out to be a mistake -- my custom IP block needs this.

Also under "peripheral I/O" pins I disable Ethernet-0. I run block automation, and it makes connections to DDR and FIXED_IO.

A new AXI peripheral

I use "Tools" at the top and launch "create and package new IP". I select "new AXI4 Peripheral" and simply name it "leds". This will be a "Lite" slave with 8 registers. It wants to call it S00_AXI -- I am tempted to change this, but leave it be (the "S" is for slave). I select "Edit IP" rather than "Add IP to the repository" just to find out what that is all about. And I Finish.

The Edit IP causes it to make a whole 'nuther Vivado screen. I try giving "Tucson Tom" as the Vendor, but it wants a domain name. So we go with "cholla.mmto.org". I also give it a nicer description, then select "Review and Package. It puts it into /home/tom/vivado/ip_repo as "s9_leds_1_0". It asks if I want to close the project, I click Yes and the second Vivado Screen goes away.

Now let's add this to our block diagram. It is not available via the "+" to add IP. We need to go to "Settings" -- IP Defaults and add to the IP repository search path. Now the "+" finds "leds_v1.0". I add it, but it does not offer to let me run block automation. It turns out (see above) that this is because I disabled the AXI GP0 interface, which actually is needed for my custom block. I double click Zynq again, turn it back on, and it offers to let me run block automation.

The address map shows 0x43c0_0000 just like the last time I made a custom IP.

Wrong IP block ?

My "ip_repo" directory contains both "leds" and "s9_leds". The "+" menu to add IP only offers "leds", which actually is what I want. I have no idea why it doesn't also offer s9_leds -- and I move that into a directory "ip_repo_OLD" off to the side to avoid confusion.

Some Verilog fiddling

This goes on in the "hdl" directory. Here we have: 
  448  2031 16218 leds_v1_0_S00_AXI.v
   78   214  2204 leds_v1_0.v
The little file sets up signals that go to the outside world, the action happens in the big file. I edit the big file outside of vivado using vim. Indeed there are 8 registers. I make the reset value to register 0 to be 32'h0abc0001. I disallow writes to this register.

To be sure that I will get my changes, I delete this block, then add it again. Now I go to Sources, select "design_1" and use the menu to select "generate HDL wrapper". Now it is on to "run synthesis". This is when I find out about stupid typos in verilog files or verilog syntax errors. But it works! Now "run implementation". We select "generate bitstream" and we are ready to test.

We haven't done much, but just seeing that we can read our ID code from our first register will be worthwhile and a good sanity check before moving on.

We have a very simple Kyu driver, which we can use as-is to display the ID code. We just need to rebuild Kyu to include the new bitstream. We edit the Makefile to change the path to copy the bitstream, then: 

make get_bit
make
cd ..; make
And we see: 
AXI reg 0 = 0abc0001

Add a 4 bit wide output that will connect to the LED

We will need to make this external and also add a constraint file, but first let's add the output.
I add these lines to the "little" file: 
// output wire  s9_leds[3:0];
output wire [3:0] s9_leds;
assign s9_leds = 4'b0000;
Now I go through the usual gyrations of refreshing the IP catalog, deleting the block from the model and adding it back again -- but no output port for the LED appears on the block diagram. Hmmm.

I go back to study some tutorials. It works for them. I see that the IP packaging edit gadget has a tab labeled "ports and interfaces". That seems suspicious, maybe I am supposed to do something there and maybe my tutorial just skipped over that.

I go to my block, pull down a menu and I see: "Edit in IP packager", this indeed takes me back to the editing GUI I used when I created the block. Now Vivado gets in a snit about my package being out of date because I have the editor running. I manage to get it to go away for now, by telling it to "automatically pick top module". I was hoping to find my output signals "s9_leds" here someplace, but no such luck.

Why doesn't it "just work"?

Start over entirely

After spending some time trying things I don't trust what I have, so I exit vivado and delete both the project and the custom IP. Now we will start over. This time, along with doing the ID register thing, I am going to set up (or try to) a single input signal "clock_50" that will someday showhow get connected to the first fabric clock.

I change the name (slightly) of both the project and the custom IP to s9_leds2 and s9leds. I now use an ID of 32'h0abc0002. Again, the clock_50 signal does not appear on the block diagram.

I figure I will just try synthesis. I create the HDL wrapper, then run Synthesis and get an error I have never seen before: 

xilinx.com:ip:axi_protocol_converter:2.1> is not supported for the current part.
So, we are spiraling downhill. It is surprising that we had success with our first simple project that just put an ID value in the first register.

Enough for one night. I thought this would be fairly easy.

Feedback? Questions? Drop me a line!

Tom's Computer Info / tom@mmto.org