May 16, 2026

Antminer S9 board - an i2c driver

This is more than just an i2c driver. It involves, first of all finding IO pins on the board for the required signals.

The i2c interface is a 2-wire interface with clock and data (SCL and SDA), so we will need two pins.

The Zynq has two i2c interfaces.

MIO on the Antminer S9

The S9 has nine 18 pin connectors. These are called "hashboard" connectors on the schematic. Each of these has one MIO signal and six signals from the PL (FPGA fabric). So we have 9 MIO signals along with 54 PL signals. The MIO signals are MIO 28 through MIO 36. On each connector, pin 18 has the MIO signal.

My Antminer boards have pins soldered to J2, J3, and J4. For some reason J1 was skipped. Probably because it was near the edge of the board. This makes it convenient for me to use the MIO signals on J2, J3, or J4 for this i2c experiment.

To get i2c signals onto these pins, we need to configure the MIO pin registers in the SLCR (system level control register) section. The relevant pages of the TRM for this are pages 1660 through 1662. It turns out that only i2c-1 is available on J2 (MIO 29), but MIO 30 and 31 give me the signals I want for i2c-0 as follows: 

J3 pin 18 -- MIO 30 - i2c-0 clock
J4 pin 18 -- MIO 31 - i2c-0 data

The TRM in chapter 20 discusses the i2c controller and has a diagram showing the possibility to route i2c signals to EMIO and thus into the PL. It says plainly, "The I2C SCL and SDA signals can be routed to one of many sets of MIO pins or to the EMIO interface." See pages 623 to 624 in the TRM. Making use of this would be something for yet another day.

Feedback? Questions? Drop me a line!

Tom's Computer Info / tom@mmto.org