Before I forget one very important point, let me mention it up front. The STM32 (or the Cortex -M3 and -M4) have a behavior that surprises me. Interrupts are not automatically turned off inside of an interrupt handler! I come from experience with Cortex A chips where this is most definitely the case and something I expect and rely on. This has yet to bite me, but it is worth keeping firmly in mind. One interrupt can interrupt another, and I have even seen code that masks of the interrupt being handled, presumably so that another interrupt of the same sort doesn't come along and cause some crazy race. All this is something I have never had to think about before and one of the reasons that Cortex-M programs get fussy about setting interrupt priorities in the NVIC.
That aside, what about USB interrupts. We have no end of interrupts. In fact the driver is all about interrupts. We have endpoint interrupts feeding interrupts feeding yet more interrupts, with various masks all along the way. Think of a tree. One interrupt ultimately exits the USB subsystem and we have one bit on the AHBCFG to mask it on or off. Above that we have a 32 bit status and mask register pair to decide what interrupts are active and manage them. But two of those interrupts are from endpoints (in and out), and each endpoint can produce a variety of interrupts, so we have ways to figure out which endpoint interrupted and to mask off the various endpoints, and for each endpoint to mask off its various sources.
It is worth noting that section 22 of the reference manual (the chapter on the USB subsystem) is marked "Copyright 2005, Synopsys". So this USB silicon appears to have been designed by a third party. A quick scan online doesn't turn up any gold mine of overview manuals.
Tom's Computer Info / tom@mmto.org