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The STM32H7 bare metal project -- clocks

The CPU runs off of "sys_ck" and this signal is driven by a mux which can select one of 4 clock sources:

• HSI - high speed internal RC clock
• HSE - high speed external clock (probably a crystal)
• CSI - low power RC clock (4 Mhz)
• PLL - from PLL1 R

There is also LSI, a 32 kHz crystal derived clock, but this is not available as a CPU clock source.

What about the UART clock?

The RCC_D2CCIP2R register has a field USART16SEL[2:0] that selects the clock source for USART1 and 6. As you might expect, this register is all zeros on power up. This selects rcc_pclk2 as the UART clock source.

This is configured through a fairly complex path, being derived from the 64 Mhz sys_ck. First sys_ck gets divided by D1CPRE which is a field in the RCC_D1CFGR register. This register is all zeros on power up. D1CPRE is the "D1 domain Core prescaler" and a value of zero indicates that the clock is not divided (a factor of 1). This same register also holds HPRE, which is the "D1 domain AHB prescaler". Again, a value of zero indicates that the D1 domain core clock is not divided to yield the AHB1 and AHB2 clocks. Finally, the AHB2 clock is divided by D2PPRE2 to get rcc_pclk2. As you might expect, this is also 0, so the 64 Mhz sys_ck makes its way through intact to give us pclk2.

This will of course need to be reworked when we get the CPU clock running at 480 Mhz -- the game will be like this:

• Get the HSE on to give us an 8 Mhz clock
• Configure PLL 1 to bump that up to 480
• Select PLL 1 as sys_ck
• Leave D1CPRE dividing the clock by 1 to get 480 for "CPU1"
• Let HPRE divide this by 2 to get 240 for "CPU2"
• Divide this by 4 to get 60 Mhz for APB1 and APB2
• Do the same to get 60 Mhz for APB4

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