October 12, 2026
First experiences with STM32 CubeMX -- RAM on the STM32H7 series
Before actually talking about ram, we need to talk about power domains.
The chips has three:
- D1 - the M7 core, main SRAM and flash
- D2 - most peripherals, D2 SRAM, and the M4 core (if we have one)
- D3 - low power, limited
Each domain has a "bus matrix" that connects things.
The D1 domain has a 64 bit path, while D2 and D3 have a 32 bit path.
The D1 bus matrix is a 64 bit AXI bus matrix.
It has a connection to the D2 AHB 32 bit bus matrix.
Both ethernet and USB live in the D2 domain.
Here is a quick overview of RAM
- 64K of ITCM ram
- 128K of DTCM ram
- 512K of D1 SRAM
- 288K of D2 SRAM
- 64K of D3 SRAM
- 4K of backup SRAM (in D3)
The TCM ram (TCM = tightly coupled memory) is fast memory that runs at
the same speed as the processor core. It is a lot like an L2 cache,
but it can be accessed just like plain old memory.
Remember that these chips also have a 16K I and 16K D cache,
which do not act like plain old memory.
Memory map
We have a 4G (32 bit) address space.
I am entirely ignoring the possible M4 core for now.
0x0000_0000 to 0x0000_ffff -- ITCM (64K)
0x0800_0000 to 0x080f_ffff -- Flash bank 1 (1M)
0x0810_0000 to 0x081f_ffff -- Flash bank 2 (1M)
0x1ff0_0000 to 0x1ff1_ffff -- system memory (128K)
0x2000_0000 to 0x2001_ffff -- DTCM (128K)
0x2400_0000 to 0x2407_ffff -- AXI (D1) SRAM (512K)
0x3000_0000 to 0x3001_ffff -- SRAM1 D2 (128K)
0x3002_0000 to 0x3003_ffff -- SRAM2 D2 (128K)
0x3004_0000 to 0x3004_7fff -- SRAM3 D2 (32K)
0x3800_0000 to 0x3800_ffff -- SRAM4 D3 (64K)
0x3880_0000 to 0x3880_0fff -- Backup SRAM D3 (4K)
0x4000_0000 to 0x5fff_ffff -- Peripherals
What the heck is "system memory"?
This is read only memory that holds a boot loader as
well as possible RSS (root security services).
You can persuade the chip to boot from this by configuring
a set of boot pins. It can boot from USB, UART, i2c, spi.
This could be useful if you did not have JTAG/SWD.
AHB SRAM3 is recommended for Ethernet and USB buffers.
It seems to me that SRAM1 and SRAM2 are equally eligible.
There are other things in the memory map, but this covers the various
sorts of memory and ignores the details of peripherals and
external memory and peripherals.
My bare metal layout
I specify flash at 0x0800_0000 and sram at 0x2000_0000, so I am using
Flash bank 1 and DTCM. I put the stack at 0x2002_0000 -- at the very
end of DTCM.
DMA controllers
The H7 chips have 4 (or 5, depending on how you count) DMA controllers.
- MDMA in the D1 domain
- DMA2D in the D1 domain
- DMA1 in the D2 domain
- DMA2 in the D2 domain
- BDMA in the D3 domain
So, if you are working with ethernet, you won't be able to transfer into
DTCM in the D1 domain.
Have any comments? Questions?
Drop me a line!
Tom's software pages / tom@mmto.org