October 17, 2026

First experiences with STM32 CubeMX -- network errata

Here is a list of things to check and address as per comments online.

MPU setup

A Cortex-M7 can include (and does on the STM32H7) a "memory protection unit". This can control 8 to 16 independent memory regions with different permissions and attributes. Because network DMA bypasses the L1 caches, it is important to mark regions used for ethernet descriptors and buffers as strongly ordere (uncached, unbuffered) device memory. This will keep the L1 cache out of the game when the CPU accesses buffers and descriptors.

Map the buffers Normal, Non-Shareable, Cache-disabled

Alternately explicitly manage cache cleaning SCB_CleanDCache_by_Addr and invalidation SCB_InvalidateDCache_by_Addr inside low_level_output and low_level_input within ethernetif.c

Avoid DTCM

Ethenet cannot do DMA from or to DTCM. Trying to do so will yield immediate faults. The recommendation is:

RTOS bug

This only pertains to cable unplug/replug when using RTOS. The link status change calls ethernet_link_thread() which calls non-interrupt safe HAL_ETH_Stop and HAL_ETH_Start and shuts down interrupts. It should call HAL_ETH_Start_IT which will reenable interrupts.

Ring buffer tail pointer bug

The calculation of the Rx ring tail buffer pointer is flawed. You might like to think that ST would have corrected this in the current version of the firmware, but who knows. The error will lead to RBU errors (receive buffer unavailable).

Look at stm32h7xx_hal_eth.c and search for tailidx -- make sure it wraps back properly 

if (descidx == 0) {
    tailidx = ETH_RX_DESC_CNT - 1;
} else {
    tailidx = (descidx - 1U) % ETH_RX_DESC_CNT;
}

Legencary STM32H7 ethernet bug fix repository

This is created by use "alister" and has custom ethernetif.c files. These threads are 5 and 7 years old, but clearly some of these things are still issues.

Have any comments? Questions? Drop me a line!

Tom's software pages / tom@mmto.org