January 11, 2026

Kyu - network - H5 emac Phy interface

Reviewing my emac driver for the H3 I have learned several things. The H5 emac is the ethernet controller in the H3 and H5 chips. The H3 used the internal Phy, meaning it was 10 or 100 Mbit only. The H5 uses an external Phy (the realtek RTL8211E) which means that it can run at 1000 Mbit.

An important note is in order at this point. I spent a lot of time with the H3 trying to understand the PHY (MDIO) interface and ultimately gave up. I simply left the PHY alone and relyed on the setup done by U-boot and turned my attention to other aspects of the emac driver. There is no reason why I could not also do this for the H5. What I should do is to split out the non-functional PHY code and save it for "a rainy day", thus cleaning up the driver.

The H5 emac and its PHY interface

The H5 emac is described in section 9.7 of the TRM (page 639). The block diagram shows MII, RMII, and RGMII signals between the emac and the Phy. The schematic shows a power enable signal, which is worth remembering. This comes from PD6, but may not need to be controlled explicitly -- it may be dealt with as a special function set up by U-boot.

There are 3 emac registers dedicated to the Phy that I can see:

MII is "media independent interface". MII is the original and does 10/100 only with 4 bits/cycle and a 25 Mhz clock.

RMII is "reduced MII". It is still 10/100 only, but has fewer pin with 2 bits/cycle and a 50 Mhz clock.

RGMII is "reduced gigabit MII". It does 4 bits/cycle, but DDR (double data rate) with a 125 Mhz clock.

(There is also XGMII for 10 Gigabit ethernet, as well as SGMII which is "serial gigabit MII" with a 625 Mhz clock and only a single differential pair for each of Tx and Rx, but we aren't dealing with these here).

MAC is "media access controller" and is the logic can converts a packet into a stream of bytes. PHY is the physical layer. The MII is the connection between the MAC and the PHY.

Selecting an external PHY

There doesn't seem to be an explicit switch just for this. The MII command register has a field to select one of 32 possible PHY devices for a given transaction.

Comments in my H3 driver (which uses the internal PHY) show that I set PHY_DEV to 1. More importantly, there is an EMAC specific syscon register that I write to as follows: 

#define EMAC_SYSCON ((unsigned int *) 0x01c00030)
*sc = SYSCON_EPHY_INTERNAL | SYSCON_CLK24 | (SYSCON_PHY_ADDR<<20);
This is described in section 4.5 of the TRM (page 162) and is called the EMAC_EPHY_CLK_REG. This is where we select and set up an external PHY.

I add some code to Kyu and print out the value left behind by U-boot: 

EMAC syscon: 00050006
If we believe this value, it indicates a PHY address of 0 and an external PHY. It also shows that RGMII is selected.

Oddly enough there is a bit to select a 24 or 25 Mhz clock. It is set to use a 24 Mhz clock, and my notes indicate that when I set it to use the 25 Mhz clock, nothing works.

Look at the RTL8211E datasheet

I use locate and find I have several copies laying around, including one in this suggestive directory: 
/Projects/OrangePi/MDIO/RTL8211E(G)-xx-CG_DataSheet_1.3.pdf
This is a 72 page document. It only describes the chip as using RGMII.

The datasheet says there are 3 pins to set the PHY address. These are PHYAD[0,1,2]. When these are set to 0, it will support (respond to?) all PHY addresses. These pins are shared with LED drive pins and the datasheet shows how things should be arranged.

The Orange Pi PC 2 schematic shows how the config pins are set up and boldly states that the PHY address is set to 001. Indeed these pins are shared with LED on the ethernet connector (two of them are) as follows:

The schematic says the green LED indicates link up/down. I see mine blinking in an irregular pattern -- and while running Kyu! At this point Kyu has no network driver, so whatever is going on is from the initialization performed by U-boot.

Have any comments? Questions? Drop me a line!

Tom's electronics pages / tom@mmto.org