January 6, 2026

Kyu - ARM - barriers and weak memory

Weak memory may be a poor choice of words. The memory is not "wimpy", rather it is flexible. And the memory itself is just plain old RAM, but the rules by which ARM handles access are flexible, i.e. weak.
Here are some links, including an interesting white paper from ARM:

Barriers

ARM provides three instructions that allow the programmer to insist on memory ordering where it is needed: 
    dmb     ish     ; data memory barrier
    dsb     ish     ; data synchronization barrier
    isb     sy      ; instruction synchronization barrier
The "isb" flushes the instruction prefetch, and you would probably use it only if you just put new code in place by reading (or paging) it from disk.

The "dmb" ensures that all preceding writes get issued, but does not stall execution.

The "dsb" does more -- it stalls until those writes are completed. This should be used sparingly, such as when context switching where you want all writes to finish before memory gets unmapped.

The arguments to these instructions are the "synchronization domain".

Have any comments? Questions? Drop me a line!

Tom's electronics pages / tom@mmto.org