March 19, 2026

Future Work

I was working on this daily through mid January of 2026. I set this aside because other things demanded my attention. There was the Tucson mineral show, a visit from my son in Sweden, as well as various home maintenance projects.

I am putting these notes together in March, as I try to remember (without perfect success) just what I was working on last.

I was doing work to understand the h5 boot process. This was complicated by trying to build components and getting unexpected errors. The idea was to be able to build ATF and U-boot from source, then add my own debug to investigate things about the network MDIO and PHY driver. But, as is often the case, what I thought would be a handy tool turned out to be a puzzle of its own.

Digging into ATF would be a study well worth the time. The code seems clean, and well written, and gives insight into ARM details that I don't find explained elsewhere.

Some web pages relevant to all of this

U-boot has some nice developer documents.

The mysterious (in the MDIO context) terms "Clause 22" and "Clause 45" talk about MDIO within the IEEE 802.3 document on Ethernet.

ARM cache stuff

A network driver that does DMA will need to deal with ARM caches. VIPT stands for "virtual indexed, physical tagged" and this is how ARM instruction caches on A-series ARM seem to be done. We probably don't care for a network driver.

ARM has an "ic" instruction that handles instruction cache operations. (is there also a "dc" instruction? Yes there is!) 

IC IALLUIS: Instruction Cache Invalidate All to PoU, Inner Shareable.
IC IALLU: Instruction Cache Invalidate All to PoU.
IC IVAU: Instruction Cache Invalidate by VA to PoU.
There is a bunch of foggy terms PoC and PoU and such that ARM seem to keep intentionally vague, because they can only be defined for a particular SoC (and they never are).
Have any comments? Questions? Drop me a line!

Tom's electronics pages / tom@mmto.org