September 28, 2026

STM32 Nucleo boards

ST makes a wide variety of STM32 ARM based microcontrollers. Some hardly seem "micro", but you can judge for yourself. When they start including ethernet controllers and floating point hardware, a person has to wonder.

How much memory do I need? I look at a pair of kyu binaries:

-rw-r--r-- 1 tom  tom   254360 Sep 27 16:32 orange.bin (for H3)
-rw-r--r-- 1 tom  tom   275880 Sep 27 16:35 h5.bin

The answer then is that 1/4M will do (256K).

ST nomenclature

A quick orientation in ST nomenclature:

F as in STM32F411 is a "foundation series" part
H as in STM32H743 is a "high performance" part

F as in STM32F411 has a cortex M4
H as in STM32H743 has a cortex M7

Other differences depend on the specific chips being compared. The M7 chips tend to support higher clock rates (400-800 Mhz, compared to 200 Mhz) and may have L1 cache. Either core can have floating point, but only the M7 cores have double precision floating point.

This survey began when I began thinking about putting an STM32 microcontroller into one or two projects I am working on. I considered the STM32F411 "black pill", but that tiny board does not have enough pins, so I would be using an i2c IO expander along with level shifters to work with it.

I was first attracted to the F411 nucleo. It sells for $18.82 at Digikey. It has a built in ST-link, as all these boards do, but no USB connector. It is Cortex M4 running at 84 Mhz (maybe 100 Mhz). You get 512K of flash and 128K of ram. You get "up to" 50 IO pins.

It is all uphill from the F411 nucleo.

The F412 nucleo caught my attention as it seems to have a network connector. This is $30.52 at Digikey. There is no network, they are just using a common board layout that is shared with other products. You do get a USB connector (with OTG FS usb) You get 1M of flash and 256K of flash. The CPU can run at up to 100 Mhz and you do get single precision floating point. You get "up to" 114 GPIO pins. All in all this is a great choice for a simple controller with a lot of IO if you don't want ethernet.

The F446 nucleo gives you 81 IO pins, 512K of flash and 128K of ram. It can run at up to 180 Mhz, but 84 Mhz is the likely default. It does include single precision floating point. The price at DigiKey is $18.82 -- the same as the F411, so this is the clear choice. However, it does not provide a USB connector.

The F429 nucleo gives you This is $38.50 at Digikey You get ethernet and a USB connector. You get 2M of flash and 256K of ram. You get over 100 IO pins. You get an M4 core running at 180 Mhz with single precision floating point.
This is dramatic step up from all other M4 based devices we are looking at, but for $2 more, the H743 looks like a far better choice.

The F756 nucleo gives you both ethernet and usb connectors. The price at Digikey jumps up to $34.39 You get 1M of flash and 320K of ram. The cpu runs at 216 Mhz. All 144 pins of the chip are exposed on the connectors. You get an M7 core with single precision floating point.

The F767 nucleo gives you both ethernet and usb connectors. DigiKey sells these for $34.39, so this is the choice so far. You get 2M of flash and 512K of ram. The cpu runs at 216 Mhz. You get 114 IO pins (out of the 144 pin package). You get an M7 core with both single and double precision floating point.

Now on to the H-series.

The H743 nucleo sells for $40.81 at Digikey. I have one of these! You get 2M of flash (dual bank) and 1M of ram. The cpu runs at 480 Mhz. You get 114 general purpose IO pins.

The H753 nucleo sells for $40.81 at Digikey. You get 2M of flash (dual bank) and 1M of ram. The cpu runs at 480 Mhz. You get 114 general purpose IO pins.

The main addition to the H753 is hardware crypto acceleration along with secure boot. This makes the H743 the smart choice for me.

The H723 nucleo sells for $40.81 at Digikey. You get 1M of ram and 564K of ram

The H755 is a dual core option. You get ethernet and usb Price is 43.53 at Digikey You get 2M of flash, 1M of sram. You can share or partition the memory. One core is an M7 running at up to 480 Mhz. The other is an M4 running up to 240 Mhz. The M7 has double/single floating point, the M4 only single. The M7 has an L1 cache split 16K I and 16K D.

The middle "5" in H755 and H753 indicate that both share the same crypto features.

What I have now

H743 nucleo (see above)
F429 discovery
F746 discovery

Conclusion

Of course, now that I make my choice, I find the H743 discontinued. I could go with the H753, but for only a few dollars more I could get the H755. I don't necessarily need to use all the features.

I have already started some work with the H743, so I have a bit of a start. I had called this the "horse pill".

Some AI comments push me towards the H753, when I ask for a comparison, as follows:

STM32H753: Massively reduces software complexity. You only maintain a single linker script, one toolchain instance, a unified interrupt vector table, and you don’t have to deal with cross-core cache maintenance.

STM32H755: Demands continuous multi-core architecture planning. You must budget for dual-GDB debugging environments, synchronize boot sequencing, and handle cache-coherency overhead across the AXI bus matrix when utilizing shared memory buffers.

Some AI details on the H755

From an advanced perspective, the STM32H755 is highly logical but introduces significant operational friction compared to single-core parts or symmetrical multi-core systems (like the ESP32).

Here is what you will actually encounter during development:

The Real Complexity Drivers

Asymmetric Multiprocessing (AMP) Debugging:
Because it is an M7 + M4 split, you cannot step through both cores cleanly in a single debugger instance. You have to spin up two separate GDB server instances on different ports and attach your IDE to both simultaneously. Breakpointing shared memory operations without halting the other core can cause cascading timeout failures in your inter-core protocols.

Cache Coherency and AXI Bus Matrix:
The Cortex-M7 features a L1 data and instruction cache. If the M4 core or a DMA controller writes data to the shared AXI SRAM, the M7 will read stale data from its cache unless you strictly manage cache maintenance operations (SCB_CleanDCache(), SCB_InvalidateDCache()) or explicitly configure regions as non-cacheable using the MPU (Memory Protection Unit).

Boot Synchronization:
The cores do not boot at the exact same time by default. You have to manage hardware semaphores (HSEM) or flash option bytes to coordinate which core boots first, initializes the system clocks, configures the power management (SMPS/LDO), and safely wakes up the second core.

Linker Script Maintenance:
You will spend a non-trivial amount of time customizing your .ld scripts. For maximum performance, you have to manually map time-critical ISRs to ITCM, fast variables to DTCM, and shared buffers to specific D2/D3 domain SRAM regions.

Where Experience Pays Off

If you are comfortable with memory-mapped hardware, concurrency patterns, and hardware datasheets, you will appreciate several design choices ST made:

Hardware Semaphores (HSEM):
The 32-bit hardware semaphore peripheral makes cross-core synchronization and resource locking incredibly fast and deterministic at the silicon level, removing the need for heavy software-only mutexes.

Independent Power Domains:
The chip is divided into three distinct power domains (D1, D2, D3). If your application requires low-power states, you can put the high-power M7 core and the D1 domain into a deep sleep while leaving the M4 core running in D2 to handle real-time sensor aggregation or communications.

CubeMX Generation:
For an experienced dev, CubeMX is best treated as a register-mapping reference rather than a golden framework. It handles the initial multi-project directory structure and clock tree initialization remarkably well, saving you a few days of boilerplate setup.