October 2, 2026

STM32H755 Nucleo -- CPU at 480 Mhz

These notes are for the H743, but thus far I have found the H755 and H743 to be essentially identical. Of course the H755 has the second core.

For the H743, not all silicon supports 480. Rev V does, but Rev Y does not. Rev Y is limited to 400 Mhz. To get to 480 you configure 2 things along with setting up the PLL --

Here is example code for the PLL setup. The basic scheme is to divide down the 8Mhz clock from ST-Link to 2 Mhz, then multiply it to 960, then divide it to a clean 480. 
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // 8 MHz input from ST-LINK
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM = 4;       // 8MHz / 4 = 2MHz (PLL input)
  RCC_OscInitStruct.PLL.PLLN = 480;     // 2MHz * 480 = 960MHz (VCO)
  RCC_OscInitStruct.PLL.PLLP = 2;       // 960MHz / 2 = 480MHz (SYSCLK)
  RCC_OscInitStruct.PLL.PLLQ = 2;
  RCC_OscInitStruct.PLL.PLLR = 2;
  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; // 1-2 MHz input range
And then you have bus clocks (CPU, AHB, and APB) -- 
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;      // 480MHz / 2 = 240MHz (HCLK)
  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;     // 240MHz / 2 = 120MHz
  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;     // 240MHz / 2 = 120MHz
  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;     // 240MHz / 2 = 120MHz
  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;     // 240MHz / 2 = 120MHz
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Tom's Computer Info / tom@mmto.org