November 27, 2023

STM32H747I-DISCO "Discovery kit with STM32H747XI MCU" -- ST-Link tools

The questions is, how can I use the ST-Link built into my STM32H747I-DISCO?
I see this in my links logs (ignoring the ACM port and mass storage: 
Nov 27 10:45:54 trona kernel: usb 1-1: new high-speed USB device number 2 using xhci_hcd
Nov 27 10:45:55 trona kernel: usb 1-1: New USB device found, idVendor=0483, idProduct=374e, bcdDevice= 1.00
Nov 27 10:45:55 trona kernel: usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
Nov 27 10:45:55 trona kernel: usb 1-1: Product: STLINK-V3
Nov 27 10:45:55 trona kernel: usb 1-1: Manufacturer: STMicroelectronics
Nov 27 10:45:55 trona kernel: usb 1-1: SerialNumber: 0035001B3232510339353236
Some searching tells me that it is possible to use ST-Link V3 with openocd, but I may need to use an STM32 specific branch. Supposedly work was going on to merge the necessary features into the main branch, but we will need to see if that has been completed.

Open source

OpenOCD

A look at the files on my Fedora xx linux system show this: 
/usr/share/openocd/scripts/interface/stlink.cfg
Comments in this file mention STLINK-V3 and the list of PID values includes 0x374e, so this looks hopeful. I also see: 
/usr/share/openocd/scripts/target/stm32h7x.cfg
/usr/share/openocd/scripts/target/stm32h7x_dual_bank.cfg
I am ignoring the second "dual bank" file for now. The comment in it says: 
# STM32H7xxxI 2Mo have a dual bank flash.

So we try this: 

openocd -f /usr/share/openocd/scripts/interface/stlink.cfg -f /usr/share/openocd/scripts/target/stm32h7x.cfg
Info : auto-selecting first available session transport "hla_swd". To override use 'transport select '.
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 1800 kHz
Info : STLINK V3J10M3 (API v3) VID:PID 0483:374E
Info : Target voltage: 3.276494
Info : [stm32h7x.cpu0] Cortex-M7 r1p1 processor detected
Info : [stm32h7x.cpu0] target has 8 breakpoints, 4 watchpoints
Info : starting gdb server for stm32h7x.cpu0 on 3333
Info : Listening on port 3333 for gdb connections
Ha! This looks very promising. And the fancy multicolor LED on the board is now blinking red/green.
I type: 
telnet localhost 4444
I seem to be in business! The "halt" command works. The "help" command shows me all kinds of things, including a bunch of stm32h7x specific things.

A board file!

Look at this: 
/usr/share/openocd/scripts/board/stm32h747i-disco.cfg
The file is big (140 lines), so let's try it: 
openocd -f /usr/share/openocd/scripts/interface/stlink.cfg -f /usr/share/openocd/scripts/board/stm32h747i-disco.cfg
Warn : Interface already configured, ignoring
Error: already specified hl_layout stlink
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 1800 kHz
Info : STLINK V3J10M3 (API v3) VID:PID 0483:374E
Info : Target voltage: 3.274900
Info : [stm32h747xih6.cpu0] Cortex-M7 r1p1 processor detected
Info : [stm32h747xih6.cpu0] target has 8 breakpoints, 4 watchpoints
Info : starting gdb server for stm32h747xih6.cpu0 on 3333
Info : Listening on port 3333 for gdb connections
[stm32h747xih6.cpu0] halted due to breakpoint, current mode: Handler HardFault
xPSR: 0x01000003 pc: 0xfffffffe msp: 0xffffffd8
The help command shows a bunch of stm32h747xih6 specific commands: 
stm32h747xih6.cpu0
      target command group (command valid any time)
  stm32h747xih6.cpu0 arm
        ARM command group (command valid any time)
    stm32h747xih6.cpu0 arm core_state ['arm'|'thumb']
          display/change ARM core state
    stm32h747xih6.cpu0 arm disassemble address [count ['thumb']]
          disassemble instructions
    stm32h747xih6.cpu0 arm mcr cpnum op1 CRn CRm op2 value
          write coprocessor register
    stm32h747xih6.cpu0 arm mrc cpnum op1 CRn CRm op2
          read coprocessor register
    stm32h747xih6.cpu0 arm reg
          display ARM core registers
    stm32h747xih6.cpu0 arm semihosting ['enable'|'disable']
          activate support for semihosting operations
    stm32h747xih6.cpu0 arm semihosting_basedir [dir]
          set the base directory for semihosting I/O operations
    stm32h747xih6.cpu0 arm semihosting_cmdline arguments
          command line arguments to be passed to program
    stm32h747xih6.cpu0 arm semihosting_fileio ['enable'|'disable']
          activate support for semihosting fileio operations
    stm32h747xih6.cpu0 arm semihosting_read_user_param
          read parameters in semihosting-user-cmd-0x10X callbacks
    stm32h747xih6.cpu0 arm semihosting_redirect (disable | tcp 
              ['debug'|'stdio'|'all'])
          redirect semihosting IO
    stm32h747xih6.cpu0 arm semihosting_resexit ['enable'|'disable']
          activate support for semihosting resumable exit
  stm32h747xih6.cpu0 arp_examine ['allow-defer']
        used internally for reset processing
  stm32h747xih6.cpu0 arp_halt
        used internally for reset processing
  stm32h747xih6.cpu0 arp_halt_gdb
        used internally for reset processing to halt GDB
  stm32h747xih6.cpu0 arp_poll
        used internally for reset processing
  stm32h747xih6.cpu0 arp_reset
        used internally for reset processing
  stm32h747xih6.cpu0 arp_waitstate
        used internally for reset processing
  stm32h747xih6.cpu0 array2mem arrayname bitwidth address count
        Writes Tcl array of 8/16/32 bit numbers to target memory
  stm32h747xih6.cpu0 cget target_attribute
        returns the specified target attribute (command valid any time)
  stm32h747xih6.cpu0 configure [target_attribute ...]
        configure a new target for use (command valid any time)
  stm32h747xih6.cpu0 curstate
        displays the current state of this target
  stm32h747xih6.cpu0 eventlist
        displays a table of events defined for this target
  stm32h747xih6.cpu0 examine_deferred
        used internally for reset processing
  stm32h747xih6.cpu0 get_reg list
        Get register values from the target
  stm32h747xih6.cpu0 invoke-event event_name
        invoke handler for specified event
  stm32h747xih6.cpu0 itm
        itm command group (command valid any time)
    stm32h747xih6.cpu0 itm port  (0|1|on|off)
          Enable or disable ITM stimulus port (command valid any time)
    stm32h747xih6.cpu0 itm ports (0|1|on|off)
          Enable or disable all ITM stimulus ports (command valid any time)
  stm32h747xih6.cpu0 mdb address [count]
        Display target memory as 8-bit bytes
  stm32h747xih6.cpu0 mdd address [count]
        Display target memory as 64-bit words
  stm32h747xih6.cpu0 mdh address [count]
        Display target memory as 16-bit half-words
  stm32h747xih6.cpu0 mdw address [count]
        Display target memory as 32-bit words
  stm32h747xih6.cpu0 mem2array arrayname bitwidth address count
        Loads Tcl array of 8/16/32 bit numbers from target memory
  stm32h747xih6.cpu0 mwb address data [count]
        Write byte(s) to target memory
  stm32h747xih6.cpu0 mwd address data [count]
        Write 64-bit word(s) to target memory
  stm32h747xih6.cpu0 mwh address data [count]
        Write 16-bit half-word(s) to target memory
  stm32h747xih6.cpu0 mww address data [count]
        Write 32-bit word(s) to target memory
  stm32h747xih6.cpu0 read_memory address width count ['phys']
        Read Tcl list of 8/16/32/64 bit numbers from target memory
  stm32h747xih6.cpu0 rtt
        RTT target commands
    stm32h747xih6.cpu0 rtt channellist
          list available channels
    stm32h747xih6.cpu0 rtt channels
          list available channels
    stm32h747xih6.cpu0 rtt polling_interval [interval]
          show or set polling interval in ms
    stm32h747xih6.cpu0 rtt setup 
  
          setup RTT (command valid any time)
    stm32h747xih6.cpu0 rtt start
          start RTT
    stm32h747xih6.cpu0 rtt stop
          stop RTT
  stm32h747xih6.cpu0 set_reg dict
        Set target register values
  stm32h747xih6.cpu0 tpiu
        tpiu command group
    stm32h747xih6.cpu0 tpiu config (disable | ((external | internal
              ( | <:port> | -)) (sync  | ((manchester
              | uart) ))  []))
          Configure TPIU features, DEPRECATED, use 'tpiu create' (command
          valid any time)
  stm32h747xih6.cpu0 was_examined
        used internally for reset processing
  stm32h747xih6.cpu0 write_memory address width data ['phys']
        Write Tcl list of 8/16/32/64 bit numbers to target memory
stm32h747xih6.dap
      dap instance command group (command valid any time)
stm32h7x
      stm32h7x flash command group (command valid any time)
  stm32h7x lock bank_id
        Lock entire flash device.
  stm32h7x mass_erase bank_id
        Erase entire flash device.
  stm32h7x option_read bank_id reg_offset
        Read and display device option bytes.
  stm32h7x option_write bank_id reg_offset value [mask]
        Write device option bit fields with provided value.
  stm32h7x unlock bank_id
        Unlock entire protected flash device.
stmqspi
      stmqspi flash command group (command valid any time)
  stmqspi cmd bank_id num_resp cmd_byte ...
        Send low-level command cmd_byte and following bytes or read
        num_resp.
  stmqspi mass_erase bank_id
        Mass erase entire flash device.
  stmqspi set bank_id name chip_size page_size read_cmd qread_cmd pprg_cmd
            [ mass_erase_cmd ] [ sector_size sector_erase_cmd ]
        Set params of single flash chip
I try: 
stm32h747xih6.cpu0 curstate
halted
Lots to learn here.
Feedback? Questions? Drop me a line!

Tom's Computer Info / tom@mmto.org