March 2, 2025

STM32F429 Discovery Kit - first steps with OpenOCD

I have some configuration info for my F411 project, so let's give that a whirl:
I saw this when I plugged in the USB cable to the ST-Link port: 
Mar  2 16:55:43 trona kernel: usb 3-1.5: new full-speed USB device number 7 using ehci-pci
Mar  2 16:55:43 trona kernel: usb 3-1.5: New USB device found, idVendor=0483, idProduct=374b, bcdDevice= 1.00
Mar  2 16:55:43 trona kernel: usb 3-1.5: New USB device strings: Mfr=1, Product=2, SerialNumber=3
Mar  2 16:55:43 trona kernel: usb 3-1.5: Product: STM32 STLink
Mar  2 16:55:43 trona kernel: usb 3-1.5: Manufacturer: STMicroelectronics
I have some Makefile entries that look like this: 
OCDCFG = -f /usr/share/openocd/scripts/interface/stlink-v2.cfg -f /usr/share/openocd/scripts/target/stm32f4x.cfg
ocd:
	openocd $(OCDCFG)
So I try typing "make ocd" and it works! The COM led starts blinking red/green while openocd is running.
And I see this response: 
Open On-Chip Debugger 0.12.0
Licensed under GNU GPL v2
Info : auto-selecting first available session transport "hla_swd". To override use 'transport select '.
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 2000 kHz
Info : STLINK V2J36M26 (API v2) VID:PID 0483:374B
Info : Target voltage: 2.859604
Info : [stm32f4x.cpu] Cortex-M4 r0p1 processor detected
Info : [stm32f4x.cpu] target has 6 breakpoints, 4 watchpoints
Info : starting gdb server for stm32f4x.cpu on 3333
Info : Listening on port 3333 for gdb connections
This looks great. I open another terminal and type "telnet localhost 4444" and get a prompt from openocd. I type "reset", watch the LCD display and indeed it executes a reset. Then I try this: 
> halt
[stm32f4x.cpu] halted due to debug-request, current mode: Thread
xPSR: 0x61000000 pc: 0x080b2ab6 psp: 0x200212d8

> reg
===== arm v7m registers
(0) r0 (/32): 0x00000001
(1) r1 (/32): 0xa5a5a5a5
(2) r2 (/32): 0xa5a5a5a5
(3) r3 (/32): 0xa5a5a5a5
(4) r4 (/32): 0x20000354
(5) r5 (/32): 0xa5a5a5a5
(6) r6 (/32): 0xa5a5a5a5
(7) r7 (/32): 0xa5a5a5a5
(8) r8 (/32): 0xa5a5a5a5
(9) r9 (/32): 0xa5a5a5a5
(10) r10 (/32): 0xa5a5a5a5
(11) r11 (/32): 0xa5a5a5a5
(12) r12 (/32): 0xa5a5a5a5
(13) sp (/32): 0x200212d8
(14) lr (/32): 0x080af7cf
(15) pc (/32): 0x080b2ab6
(16) xPSR (/32): 0x61000000
(17) msp (/32): 0x2002f018
(18) psp (/32): 0x200212d8
(20) primask (/1): 0x00
(21) basepri (/8): 0x00
(22) faultmask (/1): 0x00
(23) control (/3): 0x02
(42) d0 (/64): 0x0000000000000000
(43) d1 (/64): 0x0000000000000000
(44) d2 (/64): 0x0000000000000000
(45) d3 (/64): 0x0000000000000000
(46) d4 (/64): 0x0000000000000000
(47) d5 (/64): 0x0000000000000000
(48) d6 (/64): 0x0000000000000000
(49) d7 (/64): 0x0000000000000000
(50) d8 (/64): 0x0000000000000000
(51) d9 (/64): 0x0000000000000000
(52) d10 (/64): 0x0000000000000000
(53) d11 (/64): 0x0000000000000000
(54) d12 (/64): 0x0000000000000000
(55) d13 (/64): 0x0000000000000000
(56) d14 (/64): 0x0000000000000000
(57) d15 (/64): 0x0000000000000000
(58) fpscr (/32): 0x02000000
===== Cortex-M DWT registers
That is enough for a start. I'll have to give myself a refresher on openocd and learn about the F429 address map before I can do more. Feedback? Questions? Drop me a line!

Tom's Computer Info / tom@mmto.org