March 28, 2025

Black Pill boards - F411 USB hardware -- part 1, addresses

Exactly a month ago I wrote a couple of pages on F411 USB hardware. Now I want to look at the F429. Don't panic! The F429 has two USB interfaces, one FS, the other HS. The two are very very similar. The FS interface in the F429 is exactly the same as the F411

It all begins with device registers, at least for me. These are located at: 

0x5000_0000 for FS
0x4004_0000 for HS
A 256K address range is allocated to each device. For the FS, it is on the AHB2 bus, for the HS, it is on the AHB1 bus.

The register layout is like this: 

0000 - core registers (1K)
0400 - host registers (1K)
0800 - device registers (1.5K)
0e00 - power and clock registers (0.5K)

1000 - endpoint 0 (4K)
2000 - endpoint 1 (4K)
3000 - endpoint 2 (4K)
4000 - endpoint 3 (4K)
 .. this is the end of endpoints for the FS device.
5000 - endpoint 4 (4K)
6000 - endpoint 5 (4K)
 .. the HS device has 2 more endpoints

2_0000 - direct access to FIFO ram (128K)
The address for direct FIFO ram access is never used by the current driver. The TRM states that it is for debug.

Note that the device can operate either in device or host mode. We always use it in device mode, so we can ignore the host registers. In fact an error will be flagged if we try to access host registers while in device mode. So, how many registers are we dealing with? 

core (global) registers - 15+N
device registers - 15
power and clock - 1
As near as I can tell there is just one register for each endpoint that gives access to the endpoint FIFO. You can read it (for an OUT endpoint) or you can write it (for an IN endpoint). Nothing could be simpler. Once again, we have a generous 4K address spece with just one 32 bit register located at the start of it.

All register accesses, including the fifo are 32 bit reads and/or writes.

FIFO contents

A fifo with incoming data will have a 32 bit header followed by the data.

For data received (an OUT endpoint), the header looks like: 

int32_t epnum : 4;
uint32_t bcnt : 11;
uint32_t dpid : 2;
uint32_t pktsts : 4;
uint32_t fn : 4;
uint32_t Reserved : 7;
This is in USB_OTG_DRXSTS_TypeDef in the current code.

There seems to be no such header for data being sent (Tx on an IN endpoint). It is handled entirely differently.

Feedback? Questions? Drop me a line!

Tom's Computer Info / tom@mmto.org