July 3, 2017

The ARM Cortex M3

I am working with an STM32F103C8T6 device, which contains an ARM Cortex-M3 processor.

The Cortex-M3 runs only in thumb mode!

Bit Banding

Due to the lack of instructions to set and clear individual bits, this processor has a unique feature called "bit banding" regions. This is pretty simple once your brains stops rattling around when you first hear about it.

The idea is this. There are two such regions.

One maps 1M of SRAM (which starts at 0x20000000).
The other maps 1M of Peripherals (which start at 0x40000000).

The SRAM region is mapped to a 32M region starting at 0x22000000.
The Peripheral region is mapped to a 32M region starting at 0x42000000.

If you write a 0 or 1 to a 32 bit word in the band region, the corresponding bit in the "real world" region gets cleared or set, and this is done using an atomic read-modify-write.

So, if you want to clear the first bit of the word at address 0x20000000, you write a zero to 0x22000000. To clear the next bit, you write to the word at 0x22000004. You increment by 4 since you are dealing with 32 bit words in the bitband region.

Cortex-M3 Peripherals

These are things that are part of the Cortex-M3 core that you might expect to be either part of an SoC or handles via the Coprocessor interface on a Cortex-A chip.

Take a look at Chapter 4 of the Cortex-M3 reference manual. Here is a list, perhaps not complete:

These are at a base address of 0xe000e000.
The system control block is a grab bag of things, including items like the vector table offset register.

The NVIC is absolutely crucial if you want to use interrupts.

Feedback? Questions? Drop me a line!

Tom's Computer Info / tom@mmto.org