A peek at the schematic shows that USART1 is connected to the ST-Link controller via PA9 and PA10. These port pins are familiar from my work with F103 and F411 chips. This seems too good to be true.
The schematic shows a big red "X" across these two lines, which worried me at first. This is not a concern. The big "X" is across jumper JP4 which indeed is on the PCB, but is not populated. The idea is not that you would short these together, but that you could solder a header on here, and get access to the serial signals (getting ground someplace else). Good to know about, but nothing I will be eager to do anytime soon.
The data sheet says that we have "up to" 4 usart devices, then goes on to say that we have 4 usart devices and 4 uart devices. The plot thickens. Table 2 on page 16 shows exactly what each chip has. We have a 32F429ZIT6 which does have 4 and 4. It also has 114 GPIO signals, which is worth knowing.
We have 4 usarts (1,2,3, and 6) and 4 uarts (4,5,7, and 8).
Usart 1 and 6 can run the fastest (up to 5.62 Mbit/s with 16x oversampling), and are on a 90 Mhz APB2 bus.
usart1 is at 0x4001_1000 - 0x4001_13FF gpioA is at 0x4002_0000 - 0x4002_03FF USB OTG FS is at 0x5000_0000 - 0x5003_FFFF USB OTG HS is at 0x4004_0000 - 0x4007_FFFF RCC is at 0x4002_3800 - 0x4002_3BFFThese are all the same as the F411 (except the F411 does not have USB OTG HS). This is surprising, and also very nice, as I may just be able to run F411 code on the F429 without changes.
Flash and SRAM addresses can be mapped in various ways depending on boot mode.
Currently, my linker script for the F411 is set up like this:
flash(RX) : ORIGIN = 0x08000000, LENGTH = 512K sram(WAIL) : ORIGIN = 0x20000000, LENGTH = 128KIt remains to be seen if this will simply work with the F429. If not, read pages 70-72 in the TRM carefully
Tom's Computer Info / tom@mmto.org