January 31, 2022

Orange Pi 4 (Rockchip 3399) USB Synopsys, dwc drivers

The tragedy here is that Synopsys has not made public documentation that is essential for programming these devices. The RK3399 TRM documents registers and the bits within them, but has nothing about data structures in memory that are crucial to programming these devices. Some things can be learned by studying the linux drivers, but mysteries still remain.

This is sad situation. It makes an interesting contrast to Texas Instruments, ARM, or Xilinx; all of whom publish exquisite documentation. Synopsys does have documentation. Who knows how good it is, because a person like me can't get access to it.

Rockchip RK3399

This is where this whole business started. I began getting a deja vu feeling studying the RK3399 USB 3 driver. It turns out this uses a USB design known as the "Synopsys Designware" usb core. And it turns out there are two versions, one for USB 2.0 and the other for USB 3.0

Linux has drivers for each, and they are different. You find them at: 

drivers/usb/dwc2
drivers/usb/dwc3
Both are OTG drivers. What OTG means is that the device can assume either a host or a device role. If software allows it, the device can switch roles as needed.

Take a look at the driver source, along with:

A lot of ARM chip makers like to use the "designware" cores, and I decided to make an inventory of them. It is not always indicated or obvious that a chip is using a designware core. Here are my clues for finding out. I look at the device registers.

The USB 3.0 designware core has a set of standard xHCI registers at the start (offset 0)
Then there are global (core) registers following, at offset 0xc100 in the RK3399.
Then there are device registers after that, at offset 0xc700 in the RK3399.

The USB 2.0 designware core has global (core) registers first, at offset 0.
Then there are host registers at offset 0x400.
Then there are device registers at offset 0x800.

NetBSD drivers

These are often much easier to study than linux drivers.

Take a look at: 

sys/external/bsd/dwc2 is a driver for the Synopsys Designware USB IP

A survey of chips and devices

STM32H743 - dwc2 HS/FS OTG
STM32F4xx family - dwc2 HS/FS OTG
STM32F103 - FS device only (older dwc ??? )
BBB - not DWC - Mentor OTG HS/FS
Orange Pi H3 boards - not DWC - OTG HS/FS ohci/ehci
Orange Pi H5 boards - not DWC - OTG HS/FS ohci/ehci
Fire3 Samsung S5P6818 HS/FS USB2 OTG - probably dwc2
Fire3 Samsung S5P6818 HS/FS USB2 host - ohci/ehci
RK3328 - one dwc2 and 2 others unknown
RK3399 - two dwc3 USB3 OTG interfaces
RK3399 - two x USB2 host fs/hs interfaces

A side-track on the RK3328

An unhappy situation with the RK3328 is that I am unable to find part 2 of the TRM online, and the description of the USB hardware is contained there. I look at the linux "dtsi" file and discover: 
usb20_otg: usb@ff580000 is dwc2
usb_host0_ehci: usb@ff5c0000 is generic-ehci
usb_host0_ohci: usb@ff5d0000 is generic-ohci
The datasheet mentions that the RK3328 has a USB3 host that is xhci, but says nothing about OTG. It is odd that the linux dtsi makes no mention of it. The RK3328 trm (part 1) shows the address map with the 3 entries above, and also an entry at ff60_0000 that is labeled "usb3_otg".

It is worth noting also that the Orange Pi board I have with the RK3328 (the Orange Pi R1 plus LTS) has a USB-C port.

On the R1 LTS, the usb2 otg is connected to the USB-C connector. The usb3 is connected internally to the second ethernet (which does make sense given that usb3 can do 5G/s) The usb2 host ehci/ohci goes to a typical usb host connector

Indeed the RK3328 usb3 is a dwc3 device. This note (circa March, 2019) indicates there are issues with the PHY device handling disconnects. This would certainly not seem to matter when the usb3 is hard-wired to the usb-ethernet chip on board.

Various rubbish related to Designware USB

Bear in mind when looking at information on the internet that dwc2 and dwc3 both exist and are different. I found the following resources before I understood this and spent some time doing head scratching before I sorted this out.

Also note that "SuperSpeed" implies USB 3.0

The above link on Github is by a guy who worked out details without proper documentation by studying code in Apples SecureROM for the iPhone 8.
Have any comments? Questions? Drop me a line!

Tom's electronics pages / tom@mmto.org