December 7, 2025

My notes on the GIC 500

These are my notes as I work my way through the 930 page PDF entitled "ARM GIC Architecture Specification version 3 and 4". I have learned that it pays off in a big way, to just slow down and take the time to learn what you need to learn in cases like this. I intend to ignore GIC v4 entirely in this document.

PE is "processing element - namely an ARM 64 bit core that expects to receive and handle an interrupt.

We have these interrupt sources --

PPI are tied to a specific core (such as a timer that only a certain core should respond to). SPI can "float" between cores (such as ethernet interrupts).

SGI are intended for interprocessor communication. I often use them for diagnostics and testing. An SGI can target multiple PEs.

It is possible for an SPI to target multiple PE, but only one responds and actually handles the interrupt.

The GIC document calls these INTID values (not IRQ as I always have). Since PPI are unique to each processor, each processor can use the same PPI number for different events. There is not need to use a distributor to route these, whereas for SPI the distributor must specify which PE is expected to handle the interrupt.

Remember that the PE receives only one of two things. A IRQ or a FIQ signal. It is the GIC that handles the multitude of actual interrupt sources.

The issue of Secure versus Non-secure state can complicate matters.

The GIC can handle "virtual interrupts", which has to do with hypervisors running at EL2 and various VM running at EL1.

GIC v3 can now handle 128 PE's, whereas GIC v2 could only handle 8. This is not anything I am currently dealing with, but is one of the motivations ARM had for developing GIC v3. Two things were introduced in connection with this, affinity routing and the new "Redistributor" component of the GIC.

Interrupt grouping is an attempt to relate to the EL business. Group 0 gets handled at the highest level (no doubt EL3). Then we have Secure and Non-secure Group1.

ITS is new with GIC v3 (Interrupt Translation Service). If used, it always generates LPI, which are message-based interrupts.

LPI are new and optional and relate to the ITS.

GIC v3 can use system registers (that work with the MRS and MSR instructions) in lieu of memory mapped registers. This can allow more generic code to be written that doesn't need to know the GIC adress on a specific system.

GICD, GICR and GITS registers are always memory mapped.

GICC, GICV, and GICH can be memory mapped for legacy, but get replaced by system registers when system registers are enabled.

System register names have the prefixes ICC, ICV, and ICH.

Routing

The Distributor routes SPi.
The Redistributor routes PPI and SGI.

Affinity routing uses the Aff fields in the MPIDR to identify PE nodes.

GIC partitioning

IRI = Interrupt Routing Infrastructure.

An IRI is made up of the Distributor, Redistributor, and ITS.
Note that the ITS is optional.

The Distributor is common, but there is one Redistributor per PE. There is also one CPU interface per PE.

An SPI goes from the source, to the distributor, to the redistributor, to the CPU interface, to the PE.
A PPI goes directly to the redistributor.

Register maps

The bulk of the 930 page GIC document details the programming model (pages 185-839).
Have any comments? Questions? Drop me a line!

Tom's electronics pages / tom@mmto.org