Orange Pi 4 (Rockchip 3399) My notes on the GIC 500 manual

The GIC document is an official specification from ARM and is full of all kinds of acronyms. It appears to me that v3 and v4 are almost identical, but v3 is a significant change from v2.

The GIC-500 supports up to 128 cores and only works with ARMv8 (64 bit) processors. It complies with version 3.0 of the GIC architecture specification.

"PE" is a mysterious acronym in the GIC document. It stands for "processing element" and refers to an individual CPU core (or whatever else might want to receive an interrupt).

The term "banked register" refers to a register that is a different register for each PE, but appears at the same address for each.

The GIC-500 now has a "Redistributor" which seems to take the place of the "Cpu" interface that we had in the GIC-400 (but I also see mention of a "Cpu" section, so stay tuned). All the registers in the CPU section are banked, but some registers in the distributor for PPI are banked.

"D" is the distributor.
"R" is a redistributor (there is one for each PE)
"C" is a CPU interface (also one for each PE)

With the GIC v2 (GIC-400), you had a distributor and a CPU interface for each core and were done. A look at the D and C registers for the GIC-500 shows that they are quite similar to the GIC-400, which is a pleasant surprise.

The ITS is an "interrupt translation service". It is optional, and translates events into LPI (local peripheral interrupts). The ITS along with the distributor and redistributor are refered to a an IRI (interrupt routing infrastructure).

We have the following 4 sources of interrupts:

• SPI - shared peripheral interrupts (what you are usually interested in, from a specific hardware item)
• PPI - private peripheral interrupts (restricted to numbers 16-31)
• SGI - software generated interrupts (you write to a register in the GIC to generate these)
• LPI - local peripheral interrupts - who knows, new for v3 and v4 and go through the ITS