Enabling the cache requires setting up the MMU. Why? Because we don't want to cache everything in the entire address space (in particular, we don't want to cache device registers).
What about spin locks when multiple cores have caches enabled? This just works because of snooping. The cache system has been very careful to make this work.
What does not work predictably is when one core has caches enabled and another does not. Coherency may be undefined in such a situation The design expects all the cores to have caches enabled and does not provide for the case when not all do. Consider this note:
He says: "Originally I had been enabling onboard caches (actually, just L1 with separate I and D, for OMAP4460) on CPU0 prior to SMP initialization and attempting to bring up the auxiliary CPUs using a global variable for synchronization until they were ready to enable caches themselves. This led to all sorts of wacky problems with memory not appearing as it should. I tried various schemes of cache invalidation and clean-up before finally just disabling caches for the purpose of bootstrapping auxiliary CPUs."So the thing to do may be to just disable all caches, get all the processors up, then enable the caches.
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Tom's electronics pages / tom@mmto.org