A lot of the chip registers and layout are the same for the H3 chip and H5 chip. It is almost as if they dropped the 64-bit ARM core into the SoC and spliced it into all the peripherals. This means that I am simply recompiling a lot of my H3 code and finding that it just runs.
I have to be careful with variable types. In particular, "long" is now a 64 bit item. The compiler treats "int" as 32 bits on both ARM 32 bit and 64 bit. The smart thing to do is to use typedefs for things like "u32" and such to avoid chasing all kinds of bug related to this.
I drag out my "Fire3" board and verify that the Kyu can initialize the timer and get interrupts on some board with a 64 bit ARM chip. Then I look at board.c and verify that I initialize the timer after I initialize the GIC, that is all OK.
So I drag out my PC 2 board, do a fresh rebuild of Kyu and fire it up. Indeed I am not getting timer interrupts.
I have a test already coded up to check if the timer is running. It is. At least the t0_cval register is changing value each time I look at it. And the irq_status register is setting a bit as it should, and I can clear that bit by writing a "1" to it. So the timer itself seems to be running and acting as it should. Setting up the serial port to generate interrupts also seems to fail (although it worked great on the H3).
Writing some code to look at GIC registers, the ISR registers are all zero. Some bit should be set showing an interrupt coming in from the timer. All this indicates that the GIC is not functioning. Also I try setting a bit in the "eset" registers, but it will never set.
I double check that I have the base address of the GIC correct:
GIC dist base: 01c81000 GIC cpu base: 01c82000
I discover a bit in a CCU register that bypasses the GIC and I get excited. And it turns out that this bit is set (bypassing the GIC on boot). So I clear it, and still nothing works. This is at:
GIC bypass currently is: 01700028 --> 00000000The base address 0x0170_0000 is described in section 4.4 of the manual. Offset 0x28 is "general control register 0", which has a default value of 0x00000010 which exactly sets the bypass bit (which is supposed to route all interrupts to the processor, so we should get interrupts either way?
There is another set of registers at 0x01c00000, but they control various aspects of the EMAC network section.
So, I am baffled. Something is keeping the GIC from running. The diagram showing clock distribution shows the GIC in the central realm with the CPU and independent of clock distribution.
Tom's electronics pages / tom@mmto.org