It turns out there is another core. With OpenRISC 1000 instructions in the middle of all this. It has its own (more or less undocumented) clock control section, and handles the activation of chip cores and so forth. It runs a blob that some energy has been spent on reverse engineering.
This is the AR100 core. The PRCM is the clock control unit associated with it.
My guess is that this is about low power sleep modes. Especially given that the power button is in this section, along with the IR receiver. No idea what all the secrecy is about.
A google search on "allwinner cpucfg" led to much of this.Qemu is an arm emulator that supports H3 Orange Pi boards (amazingly enough), so they need to emulate this section. Thus the Qemu source could be a source of information.
There is reportedly documentation in some Allwinner supplied SDK, such as for the A23 chip.
Tom's electronics pages / tom@mmto.org