January 10, 2021

Xilinx Vivado - my first project

I launch Vivado from a desktop shortcut. The shortcut apparently runs /opt/Xilinx/Vivado/2020.2/vivado. It is slow to start with lots of disk activity.

Create Project

I am following the straightforward instructions in this tutorial: I use Quick Start, Create Project.

I change the location to /home/tom/Vivado rather than /home/tom
I select RTL (register transfer language), which would be appropriate for Verilog.
I click "next" on sources and constraints.
I select my part as XC7C010-CLG400ABS-1 (where "-1" is my 667 Mhz part, -2 and -3 are faster parts, -3 is 866 Mhz).
I click Finish and I get presented with their GUI.

Resume Project

I did an exit, restarted Vivado, then tried using "Open Project". This got me nowhere, which seems like a bug or something entirely non-obvious.

However when I start Vivado, it has "recent projects" listed on the right and clicking on this gets me back to the GUI with my project.

Lingo

Apparently "synthesize" means what I would call compile, i.e. to generate the bitstream from the design files.

What they call "constraints" are all important, as they map your logic to physical connections on the chip.

Feedback? Questions? Drop me a line!

Tom's Computer Info / tom@mmto.org