FPGA - Spartan 3E board - ISE software

• ISE Webpack
• Introduction to ISE 8.2
• ISE setup on Ubuntu

A first simple project (round 2)

The idea is to simply connect a switch to an LED. On the board, we have four slide switches and 8 LED and the idea is to use the first of each set for this experiment. We also know that on the starter board, each switch or LED is labeled with the pin identity on the FPGA that is connected to it, and this is as follows:

SW0 is L13
LD0 is F12

As user "tom" I type "ise" to start the software. This launches the "project navigator", which remembers my previous project. I also get a "tip of the day", which I admire and dismiss. I will leave my old project (/home/tom/ise_zzz) alone for now. I use File -- New Project, which launches a new project wizard. I give the project the name "ise_simple" (I begin the project name with "ise" since these are becoming directories in my home page, maybe someday I should place them all into a directory of their own.

The next screen in the Wizard lets me select the Spartan-3E starter board, and doing so greys out the part number fields since it can infer those from the board selection. I make the following selections in the lower part of the window (in fact I just take the defaults):

Synthesis Tool -- XST (VHDL/Verilog)
Simulator -- ISim (VHDL/Verilog)
Preferred Language -- Verilog

Along the left side are a bunch of tiny icons, which are buttons. The uppermost is "New Source". Clicking it brings up a new source wizard. A menu of a variety of sorts of sources is presented. I select "verilog module" and give it the file name "trivial".

Now the wizard is asking me about ports for the module. I want a single bit in and a single bit out. I call these i_sw and o_led. I make o_led and output, click the "Bus" box for each, and set MSB = 0 and LSB = 0 for each. I type Next, Finish, and the "new source" wizard exits.

Now the Project Navigator is showing me a template for the verilog. I add one line to it, as follows:

assign o_led = i_sw;

Now I can process this verilog, I do this on the lower left side of th Project Navigator. I double click on "Synthesize - XST". Away it goes, and when it finishes there is a happy green check mark on "Synthesize- XST" to assure and remind me that I did this with success.

Constraints are what connect the verilog to the real world. Just above "Synthesize - XST" is "User Constraints". I click on the "+" box to expand that part of the hierarchy. Then I double click on IO pin planning, post sythesis. A popup tells me I need a UCF (implementation constraint file) to be added (that is why I am here!!) and it offers to help me make one (alternately, I could just add one if I had one). I select Yes.

I get a Welcome popup to something called "planAhead", which guides me to chapters 15, 4, 8, 7, 10, and 11 in the user guide, which is offers to me as a PDF or via the following link:

• Xilinx planahead
• Xilinx design

I know the pin numbers for my switch and LED (they are there next to the switches and LED on the board silkscreen). One column in the port display table is "Site" and that is where I want to enter my pin numbers, L13 for i_sw and F12 for o_led. I don't fully understand this interface, but if I click on the site column I get a menu from which I can select L13 and F12 as appropriate. It is showing me i_sw[0] and i_sw[1], which I don't understand, but I work with i_sw[0] and o_led[0] and hope for the best. When I am done, I click File -- Save constraints. Then I exit PlanAhead.

Now we are back to the main "project navigator". I double click on "Implement Design", it is busy for a while, there is lots of chatter in the bottom "console" window, and when done a green "ok" check mark appears.

Next I double click on "generate programming file", and am rewarded with another green check mark in short order. The console window shows me the command line it is running to do this, namely:

bitgen -intstyle ise -f trivial.ut trivial.ncd

I will note at this point that there is a file "trivial.bit" that as near as I can tell is the final result of the "Generate Programming File" step.

All that remains is to download this via USB to the board is see if it works. We know that won't be possible unless we tackle the cable drivers, so we stop here.