February 27, 2023

EBAZ4205 - blink the LED from fabric clocks 2023

I have two goals here, maybe three:

Clocks

I have read in various places that there are 4 fabric clocks. These are not independent of the PS. They must be set up. I am told this is typically done in the FSBL (first stage boot loader), but I have yet to look into that. We will pay particular attention to this aspect of things when we configure the Zynq processing system block later in this project.

It is worth noting that some boards (like the Zedboard and Zybo) have a crystal oscillator that is connected to some FPGA pin. In a case like this, the clock signal will appear in the constraint file. There is no such thing on the Ebaz and we must use fabric clocks and rely on code that runs on the PS to properly initialize them.

Starting vivado

To start vivado, I type "vivado" on the command line. This now starts vivado 2022.1.2 (since I modified my bin/vivado script).

New Project

I use File -- Project -- New which gives me a new project "wizard". I give the project a name (fabric). I let it use the usual /home/tom/vivado as the location. I call it an RTL project. There is a checkbox saying "do not specify sources at this time". I like this. It is checked and I leave it checked. The wizard does not ask me about either a constraint file or design sources now, which is great.

Select the board (not the part)

The next wizard dialog takes some care. It gives me a menu with a long list of parts, but I want to switch to "Boards" at the top of this dialog. Then I pull down the "vendor" menu and scan for "miner", when I select that, the Ebaz is the only choice (this is because I added "board files" many months ago.). Now I finish the new project dialog and I am in Vivado proper.

Add the constraint file

I am now in Vivado proper and looking at the Project Manager page. There is a "Sources" pane with a "+" on the top to allow me to add sources and constraints. I am fed up with hunting around for my constraint files at this stage and take some time to put all that I ever use in a convenient location: 
/u1/Xilinx/Ebaz_Master.xdc
/u1/Xilinx/Zedboard-Master.xdc
/u1/Xilinx/ZYBO_Master.xdc
I copy/paste the path above for the Ebaz into the form. There is now a checkbox "copy constraints files into project" which is exactly what I want.

It used to always just link to my master location, which was not good because the master has everything commented out and I need to edit it for each project. Should that ever happen again, I will note that there is as easy fix. Right click on the file to get a menu and select "copy file into project".

I double click on the file. This launches their editor. I need to go to Tools -- Settings -- Text Editor and tell it to use vim. I used to need to type :colo desert into vim, but now I am getting a reasonable color scheme and don't need to do that.

Block design

Under "IP Integrator" I click on "Create Block Design". I just stick with the default name "design_1" -- it is as good as anything and I have yet to have more than one design.

This gives me a blank "canvas" and the "+" button up top lets me add things from their "IP" collection. I use this and select "ZYNQ7 processing system" and run block automation.

Fabric clocks

Now something new. Double click on the Zynq processing system block. Who would ever guess that does something interesting? On the left side we see "Clock Configuration". We click on that and get a page with "Basic Clocking". Under that we expand "PL Fabric Clocks" and we see 4 of them: 
FCLK_CLK0  50 Mhz
FCLK_CLK1  10 Mhz
FCLK_CLK2  10 Mhz
FCLK_CLK3  10 Mhz
The initial state is that only the first clock at 50 Mhz is enabled. Just for fun, I also enable the second.

It shows a range up to 250 Mhz. I am doubtful that just changing the rate here will actually do anything (I expect that would be done by the code that runs on the PS), but again just for fun, I set the rate for FCLK_CLK1 to 100 Mhz. I finish by clicking "OK" at the bottom of the screen. Sure enough a new output for FCLK_CLK1 has appeared in the block diagram.

Now, in order to follow what I did on a prior project, I add an AXI GPIO block. When I run block automation, I select everything, then unselect "GPIO". This avoids the crazy thing trying to connect GPIO to "led_2bits". I have a nice diagram with only FCLK_CLK1 unconnected.

Add some verilog and put it into a block

The verilog I want to add is in /home/tom/blinker.v -- from a prior project with some edits. We use the "+" button in Sources, select "Add design sources" I type in the path. I see the box "copy sources into project" is checked (which makes me happy) and click Finish. I expand "Design sources" under Sources and there it is. I right click on it, select "Add module to block design" and there it is.

Back to the block design

I can click on the "canvas" background, get a menu, and select "create port". I do this twice, specify an output port for each and call them red_led and green_led. I leave the type set to "Other". Note that it is critical that these names correspond to names in the constraint file.

It is still offering to run block automation, but I ignore that. I make all the connections so that FCLK_CLK1 drives my custom block and my block drives the two ports. I call this done.

A crucial step

In the sources pane I find "design_1" (the first thing under "Design Sources"). I right click to get a menu and select "Create HDL Wrapper".

The end game

Generate Block Design
Run Synthesis
Run Implementation
Generate Bitstream
This takes a fair while. Watching the progress and status at the upper right corner of the GUI is reassuring. Note that when "Run Implementation" finishes it defaults to offering to "Open Implemented Design". I have never found this useful, so I skip it and go directly to "Generate Bitstream".

Try running it

If you haven't done it already, open a terminal window and type: 
xvcd-pico
My version will announce "Listening on port 2542" (and later "connection accepted").

Use "Open Hardware Manager", then Open target, open new target, then select Xilinx Virtual Cable. Double click on the hardware target and you should get a list of "Hardware devices". Select sc7z010_1 and then Next.

Now you should see "program device" as an option in the green bar near the top of the screen. Click that, verify the name of the bitstream file and hit return. It should give you a progress bar as it programs the FPGA, then your design should be running. It works

Conclusions

For this example, I will note that FCLK1 did not magically get set to 100 Mhz just because I selected that. Watching my LED blink, I can see that it is at 10 Mhz -- which is just what I expected.

So without fooling with code on the PS, the fabric clocks are 50,10,10,10.

I'll also note that having a few unconnected outputs did absolutely no harm. In particular not letting block automation run and invent nonsense to connect the GPIO to was just fine (and I am happy for that).

Feedback? Questions? Drop me a line!

Tom's Computer Info / tom@mmto.org