FPGA - Zedboard - my third FPGA design

Which bits? It would be nice if the lsb displayed was counting at about 2 Hz. 2^26 is 67 million, so we would like to look at bits 26-34. We will need more than a 32 bit counter, but I don't suppose Verilog would mind setting up a 64 bit counter (or a 1024 bit counter if we want one).

I launch Vivado and let it generate template files for both the verilog and the constrainsts file (those 2 files are what make up a project as we have learned). I want to learn how to use multiple verilog files and modules, but will extend my education in that direction pretty soon.

I call this project "zed_3". For the constraint file I copy from my previous "zed_2" project:

cd /u1/home/tom/zed_2/zed_2.srcs/constrs_1/imports/tom
cp blink.xdc /u1/home/tom/zed_3/zed_3.srcs/constrs_1/new/top.xdc
cd /u1/home/tom/zed_3/zed_3.srcs/constrs_1/new
vi top.xdc

Similarly, for the verilog, I copy from my previous project:

cd /u1/home/tom/zed_2/zed_2.srcs/sources_1/new
cp blink.c /u1/home/tom/zed_3/zed_3.srcs/sources_1/new/top.v
cd /u1/home/tom/zed_3/zed_3.srcs/sources_1/new
vi top.v

And it works! I had expected to have to make one revision due to making a bad guess about which bit to start with on the display, but the choice I made has the lsb changing at very nearly 1 hz.

If I get tired of watching the light show, I just flip the "enable" switch off.

Here is the verilog. Remember the input clock is running at 100 Mhz.

module blink(
    input clock,
    input enable,
    output led0, output led1, output led2, output led3,
    output led4, output led5, output led6, output led7
    );

    // 128 bit counter, why not ?
    reg [127:0] cnt = 0;

    always @ (posedge clock) begin
        cnt <= cnt + 1;
    end

    assign led0 = cnt[26] & enable;
    assign led1 = cnt[27] & enable;
    assign led2 = cnt[28] & enable;
    assign led3 = cnt[29] & enable;
    assign led4 = cnt[30] & enable;
    assign led5 = cnt[31] & enable;
    assign led6 = cnt[32] & enable;
    assign led7 = cnt[33] & enable;

endmodule

Note that verilog allows underscores in numeric constants. Such as this one:

parameter p_CNT_1HZ = 50_000_000;