EBAZ4205 - route fabric clocks to pins 2023

• Test fly my recent install of Vivado 2022.2
• Test the rates of fabric clocks 1,3,4

Starting vivado

To start vivado, I type "vivado" on the command line. This now starts vivado 2022.2.

New Project

I use File -- Project -- New which gives me a new project "wizard". I give the project a name (fabric). I let it use the usual /home/tom/vivado as the location. I call it an RTL project. There is a checkbox saying "do not specify sources at this time". I like this. It is checked and I leave it checked. The wizard does not ask me about either a constraint file or design sources now, which is great.

Select the board (not the part)

The next wizard dialog takes some care. It gives me a menu with a long list of parts, but I want to switch to "Boards" at the top of this dialog. Then I pull down the "vendor" menu and scan for "miner", when I select that, the Ebaz is the only choice (this is because I added "board files" many months ago.). Now I finish the new project dialog and I am in Vivado proper.

Add the constraint file

/u1/Xilinx/Ebaz_Master.xdc
/u1/Xilinx/Zedboard-Master.xdc
/u1/Xilinx/ZYBO_Master.xdc

I double click on the file. This launches vim with a sane color scheme.

I uncomment 3 lines for pins A20, H16, and B19.

Block design

This gives me a blank "canvas" and the "+" button up top lets me add things from their "IP" collection. I use this and select "ZYNQ7 processing system" and run block automation.

Fabric clocks

FCLK_CLK0  50 Mhz
FCLK_CLK1  50 Mhz
FCLK_CLK2  50 Mhz
FCLK_CLK3  50 Mhz

I click "OK" and it takes me back to the block diagram where I see output pins for all 4 clocks. To start with, I am just interested in the last 3.

Now I create 3 ports with names A20, H16, B19 to correspond to the pins I uncommented in the constraints file. These names are wrong but we will fix that below. I connect them to CLK1, CLK2, and CLK3.

I am not going to worry about unconnected pins like CLK0.

I am done. Note that I am adding no Verilog whatsoever.

A crucial step

It complains that M_AXI_GP0 is not connected to a valid clock source.

I add a block called "processor system reset" and run block automation.
That does not cut it.

I add an "AXI GPIO" and run block automation. This pulls in an AXI Interconnect block that gets connected to M_AXI_GP0, which looks promising. I delete the AXI GPIO block and everything looks pretty good.

And I am able to create an HDL wrapper. The final design has 3 blocks:

Zynq7 processing system
Processor System reset
AXI Interconnect

The end game

Generate Block Design
Run Synthesis
Run Implementation
Generate Bitstream

This takes a fair while. Watching the progress and status at the upper right corner of the GUI is reassuring. Note that when "Run Implementation" finishes it defaults to offering to "Open Implemented Design". I have never found this useful, so I skip it and go directly to "Generate Bitstream".

Well, the bitstream generation failed with complaints about my 3 "problem ports". It says "set property expects at least one object" and fusses about my constraints file before it gets to complaining about the ports.

The problem is pretty obvious when I look at the constraints file. The name should be "d1_5" not A20. I can always edit the constraint to give it a more friendly name (like out1, out2, out3), which I will do.

set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { d1_5 }];   # DATA1-5
set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { d1_6 }];   # DATA1-6
set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { d1_7 }];   # DATA1-7

I go back to where I would do "create HDL wrapper" and find that menu entry gone, so I try "refresh hierarchy". Then it is on to "Generate Block Diagram" and the rest of the rain dance.

And it works! and I get a proper bitstream.

Try running it

xvcd-pico

Use "Open Hardware Manager", then Open target, open new target, then select Xilinx Virtual Cable. Double click on the hardware target and you should get a list of "Hardware devices". Select sc7z010_1 and then Next.

Now you should see "program device" as an option in the green bar near the top of the screen. Click that, verify the name of the bitstream file and hit return. It should give you a progress bar as it programs the FPGA, then your design should be running. It works

Conclusions

Having a few unconnected pins did absolutely no harm.

The surprising result using the scope is that the 4 clocks are running at:

• 125 Mhz
• 25 Mhz
• 41.7 Mhz
• 41.7 Mhz

I actually went back and reconfigured the design to give me the output of CLK0 on the out1 pin. And then I verified the 125 Mhz clock rate. I'll also note that I was able to bump it up to 250 Mhz. Just what the FPGA would feel about this, I cannot say.