Xilinx Zynq - XC7Z010 - EMIO and the PL

Here is an answer from the forum post below:

They are not fixed. You just get a port at your PS7 module which says gpo[N-1:0] etc. Then you need to add a port to the top level, attach it to a pin (in an XDC) and then add a line which does the connection ala assign foo=gpo[0]; etc. For inputs a similar assign is necessary.

• EMIO to PL pins

I see other comments that say GPIO_0_0(EMIO) refers to EMIO pins in their project. This is for an example project for the ZC702

• Forum: pins needed
• Zc702 example project
• MIO and EMIO video
• How to configure EMIO
• routing to emio pins