May 15, 2022
EBAZ4205 - Xilinx Zynq - FPGA
I haven't touched my EBAZ for about a year.
Now after working with the Zedboard, Zybo, and Vivado I know a lot more
and have a much better idea about how to approach the FPGA on the ebaz.
My strategy is as follows:
- Install ebaz board files for vivado
- Locate a constraints file for the Ebaz (or work one up from the Zybo constraints file).
- Get something working as a JTAG usb connection.
- Do some things with just the FPGA (ignore the ARM) as I have done with the Zedboard.
Once I accomplish all of that, I should be able to do basic things using just the FPGA
such as blink one or both of the on-board LED.
Board files
This work has already been done and others have made this easy.
Beware in the following that the repo clones as "EBAZ4205", which is entirely likely
to overwrite things you already have on your machine.
cd /u1/Xilinx/Vivado/2021.2/data/boards/board_files
mkdir ebaz4205
cd ebaz4205
mkdir 1.0
cd /home/tom
git clone https://github.com/XyleMora/EBAZ4205.git
mv EBAZ4205/ EBAZ4205_XyleMora
cd EBAZ4205_XyleMora/Documents/"Board files"/ebaz4204/1.0
cp * /u1/Xilinx/Vivado/2021.2/data/boards/board_files/ebaz4205/1.0
That will do it. It copies:
board.xml ebaz4205.jpg part0_pins.xml preset.xml
Constraint file
A google search yields a variety of things.
But nothing that looks like a nice master XDC file of the sort available for the Zybo.
So, I may have to try to work one up from the schematic.
I am a bit surprised nobody has done this and put it up on the internet.
I can't believe I am the first one wanting to do this.
JTAG
The board has an unpopulated 14 pin JTAG header.
We need to connect something to it.
PL clock and other issues
Most of my standalone FPGA games involve some kind of clock.
And my demo boards (Zybo, Zedboard) all have some dedicated pin that
provides a clock to the FPGA (PL). I don't see anything like this on
the ebaz schematic. There is a 33.33 Mhz crystal oscillator, but it
drives "PS_CLK" as one might expect.
It turns out there are 4 clocks available in the FPGA fabric and these
can easily be accessed from Vivado. They work entirely independently
of what the PS is doing.
We have 3 "data" connectors with 20 pins each, and with inconvenient pin spacing.
These provide both Vcc and Ground, so it is relatively easy to rig up switch
inputs to these (if one ignores the connector pin spacing issue).
Actually 20 pin ribbon cables with 2mm spacing are readily available,
they just are not what I have laying around (I have 0.1 inch, i.e. 2.54mm pitch).
Feedback? Questions?
Drop me a line!
Tom's Computer Info / tom@mmto.org