makeThen when I want to burn code into flash (or ROM in the old days), I type something like:
make flashDoing things like this is part of being professional. I work on a lot of projects, and sometimes I need to work on a project after leaving it forgotten for several years. I know that I can find the source directory, edit files, and type make. I can also hand off the project to others and a proper makefile serves as a sort of documentation of how the project is built and handled.
I don't want to have to remember (or type) long command names and sequences of switches and options. Apart from the tedium of typing (and retyping when I make mistakes), I simply won't remember - and my mind is better used focusing on the problem at hand. If someone else has to jump into one of my projects, there is no substitute for the makefile.
hello: hello.c cc -o hello hello.cThere you have it, understand the above and you will understand the central concept of all makefiles. Consider the following diagram which shows the 3 components of the above two line makefile:
TARGET: SOURCE COMMANDThe thing to the left of the colon is the target, the thing we want to make.
hello: hello.c extra.c cc -c hello.c cc -c extra.c cc -o hello hello.o extra.oHere we list the sources, separated by spaces, then use as many lines as necessary to describe the process of making the target. Simple enough, eh?
make cleanMost of my makefiles have a target to handle this near the end that looks like this:
clean: rm -f hello hello.o extra.oHere there are no SOURCES, just a target, which is perfectly fine. Make will just run all the commands that follow. So you can have a target "fred" with a bunch of commands that follow and then use "make fred" to run those commands. This lets me put what would otherwise be a bunch of little random shell scripts into my makefile which both preserves them in one place and helps me be lazy.
Providing for "make clean" is a sort of good practice. The idea is to delete everthing the makefile would be able to make anyway so that typing the following is harmless:
make clean makeI have an entry to support "make term" in one of my current projects which runs the terminal emulator that I use to do debugging. Once again this is about being lazy. I don't have to remember switches and option or even the name of the terminal software.
term: picocom -b 115200 /dev/ttyUSB0
PORT = /dev/ttyUSB0This is simple enough. An assignment statement with as much white space as you care to use. This can later be referenced by wrapping it in parenthesis and slapping a dollar sign in front.
term: picocom -b 115200 $(PORT)Some people get foolishly and needlessly carried away doing this. My rule of thing is to define anything that you expect will change now and then and stick those definitions near the start of the makefile. Also define things that are used in many places.
hello: hello.c extra.c cc -c hello.c cc -c extra.c cc -o hello hello.o extra.oLet us say you just edit extra.c and then type "make". Make will look at the timestamp on the target "hello" and realize that it needs to be recompiled. If you type make again, it will do nothing, realizing it is up to date.
hello: hello.o extra.o cc -o hello hello.o extra.o hello.o: hello.c cc -c hello.c extra.o: extra.c cc -c extra.cHere if we type "make" it will try to make the first target in the file, namely "hello". It will look for the sources and decide if hello needs to be rebuilt at all, but first it looks for any dependency lines that build the sources and check if those may need to be rebuilt, going on and on as necessary.
So let's say we have built hello and left the files laying around (not running "make clean" or otherwise deleting any files). Then we edit extra.c and type make. Make will notice that extra.o is out of date and rebuild it. Then it will notice hello is out of date and relink it. However it will not need to recompile hello.c
This is no big deal on a simple piece of software like this, but consider something like an operating system built from hundreds of source files and you will see the point. Whenever "make" is processing a line with a colon separating a target from sources, it will make this timestamp evaluation. These are called "dependency lines".
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