November 2, 2019
An executive tour of the AVR architecture
If you are new to microprocessors and assembly language, this will probably be pretty hopeless.
This is written for someone who has previous experience with many processors at the assembly
level and will only discuss those aspects that uniquely characterize the AVR.
The claim is made that the C51 (Intel 8051) would have to run at 224 Mhz
to match an 8 MHz AVR. I used to use the 8051 and typically ran it at about 10 Mhz,
so the AVR at 8 Mhz is giving about 20 times the performance, which is impressive.
- There are 32 general-purpose 8-bit registers, R0–R31
- As a true RISC processor all memory access is via load/store
- A few instructions operate on 16 bit register pairs
- The last 6 register yield 3 pairs, used as pointers: X (R27:R26), Y (R29:R28) and Z (R31:R30
- The PC is a 16- or 22-bit program counter
- The SP is an 8- or 16-bit stack pointer
- SREG is an 8-bit status register
- IO registers have a dedicated 6-bit address space (hence 64 of them, 0 - 0x3f)
- Data address space maps the 32 registers, all the I/O registers (including those also accessible through the I/O address space), and the RAM
- Note that the IO registers appear both in IO space and after the registers in data space.
- The registers are the first thing in the data space.
- Data RAM will likely start at 0x100 in the data space.
- Flash has a separate address space, addressed as 16-bit words
- There are ways to access flash using the Z register pair.
This is hardly exhaustive, but gives you an overview of how the game is played.
Have any comments? Questions?
Drop me a line!
Tom's Electronics pages / tom@mmto.org