May 23, 2022

Zynq - AXI gpio

AXI gpio is one of the "prefab" IP blocks provided by Xilinx Vivado. I have been using it in a simple way by imitating what has been shown in various tutorials. I became curious what was available in the way of official documentation.

One suggestion is to fire up the SDK, right click a component, and select "IP Documentation. Also in the SDK, the BSP page has "Documention" along with "Import Examples" under "Peripheral Drivers".

Header files themselves (such as xgpi.h) are useful sources of information.

The AXI gpio has a nice product guide:

Linux drives were once described in the xilinx wiki, but that information has moved or evaporated. A Search finds it in its new location:

How does AXI gpio work?

Oddly enough you can get 2 channels. Each can be up to 32 bits wide. Each can be bidirectional by virtue of a tristate buffer. The gpio can generate interrupts.

Ignoring the interrupt capability, each channel looks like a pair of 32 bit registers.
One is the data register (read/write).
The other is the 3-state control (direction register).

What could be simpler?

Feedback? Questions? Drop me a line!

Tom's Computer Info / tom@mmto.org