Sun 3/60 - Address map

On the sun3 (and who knows yet about the sun3x) all of the IO devices are accessed through virtual addresses. In fact you can only access them after you set up the MMU and establish those virtual addresses!

The following table gives physical addresses, which seem uniform across all sun3 machines (but hold your thoughts about the sun3x):

zsc0    at obio0 addr 0x000000
zsc1    at obio0 addr 0x020000
eeprom0 at obio0 addr 0x040000
clock0  at obio0 addr 0x060000
memerr0 at obio0 addr 0x080000
intreg0 at obio0 addr 0x0A0000

After reset (and before the MMU is set up), you are unable to access RAM, not to mention IO devices. What you can acess are all the things in control space. Things like the DIAG register (LEDs), the ENABLE register, and of course the various registers that comprise the MMU.

Some (but apparently not all) sun3 machines have a UART bypass register in control space, apparently at address 0xf000_0000.

Some old notes, that need to be revised

For example the Zilog serial SCC is at 0x62000000 and 0x62002000 on the 3/80. On the 3/60 it is at 0x000000 and 0x020000!!

Actually I find the SCC for the 3/60 at 0x0fffe000 and 0x0fffe004.
This is a whole other business. We actually have to use virtual addresses to access the IO devices, and there is no telling how the rom has set up the MMU.

I have NetBSD 2.0 sources on my machine at u1/NetBSD/NetBSD-2.0.
I look at usr/src/sys/arch/sun3/conf/obio.sun3 and see:

obio0 at mainbus?

# Required OBIO devices
zsc0    at obio0 addr 0x000000
zsc1    at obio0 addr 0x020000
eeprom0 at obio0 addr 0x040000
clock0  at obio0 addr 0x060000
memerr0 at obio0 addr 0x080000
intreg0 at obio0 addr 0x0A0000

I look at usr/src/sys/arch/sun3/conf/GENERIC and see:

# Lance Ethernet (only onboard)
le0 at obio0 addr 0x120000 ipl 3

# Sun3 "si" SCSI controller (NCR 5380)
si0 at obio0 addr 0x140000 ipl 2

I look at usr/src/sys/arch/sun3/sun3/control.h and see:

#define IDPROM_BASE 0x00000000
#define PGMAP_BASE  0x10000000
#define SEGMAP_BASE 0x20000000
#define CONTEXT_REG 0x30000000
#define SYSTEM_ENAB 0x40000000
#define UDVMA_ENAB  0x50000000
#define BUSERR_REG  0x60000000
#define DIAG_REG    0x70000000

Where is the MMU? See the above! Take note of PGMAP, SEGMAP, and CONTEXT.

The enable register

#define ENA_DIAG    0x01    /* Diagnostic switch (r/o)        */
#define ENA_FPA     0x02    /* Enable floating point acc.     */
#define ENA_COPY    0x04    /* Enable copy update mode        */
#define ENA_VIDEO   0x08    /* Enable video display           */
#define ENA_CACHE   0x10    /* Enable external cache          */
#define ENA_SDVMA   0x20    /* Enable system DVMA             */
#define ENA_FPP     0x40    /* Enable MC68881                 */
#define ENA_NOTBOOT 0x80    /* Non-boot state (1 == normal)   */

/* Address of this register in control space. */
#define ENA_REG_ADDR    0x40000000