The Motorola MC6800 microprocessor
Note that the 6802 is the same as the 6800 except it
has 128 bytes of on-chip ram (at address 0), and an on
chip clock generator. The instruction set is exactly the same.
Here is a short PDF document summarizing
the 6800 instruction set.
The 6800 was an accumlator style processor with registers as follows:
- A register - 8 bit accumulator
- B register - 8 bit accumulator
- IX register - 16 bit index
- PC register - 16 bit program counter
- SP register - 16 bit stack pointer
- CC register (condition codes)
The condition codes were:
- H - half carry (carry from bit 3 to 4)
- I - interrupt mask (set if IRQ disabled)
- N - negative (set if msb of result is set)
- Z - zero (set if result is zero)
- V - overflow
- C - carry (carry from bit 7)
There is one 16 bit address space (64K) and that is it, it must hold all
RAM, EPROM, IO ports, everything.
Addressing modes:
- Implied (implicit in the instruction)
- Accumulator (data is in one of the registers)
- Immediate (8 or 16 bit data)
- Direct (one byte addresses page 0 (0000 - 00ff)
- Extended (literal 2 byte address)
- Relative (signed one byte offset added to PC+2)
- Indexed one byte is added to IX to get pointer
Apparently the 6800 included an undocumented instruction that
was dubbed the HCF instruction (halt and catch fire).
Apparently this is opcode 0xDD or 0xD9, in which the processor
continuously reads successive addresses without further instruction fetches,
and without responding to interrupts; only a reset restores normal operation.
6800 startup
There are 8 bytes of memory reserved for reset and interrupt pointers
as follows:
- fff8 - fff9 pointer to hardware interrupt handler
- fffa - fffb pointer to software interrupt handler
- fffc - fffd pointer to non-maskable interrupt handler
- fffe - ffff pointer to reset handler (this must be in ROM).
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Tom's Computer Info / tom@mmto.org