May 2, 2023

Entrex - Interface Board -- sending to the host

This is primarily a discussion of one part of the interface board schematic, but with some reference to the processor board and rom disassembly.

How is data sent from the Entrex terminal to the host, that is the question. Starting at the ROM, there are two places where the code write to port 0x70 (executes a "OUT 0x70" instruction.

One is immediately after it reads data from the keyboard. However not all data reads from the keyboard cause data to be sent to the host. Most do, but some are handled locally in the terminal.

The other always sends the data 0xAA and I am not sure what this is all about.

Another important point. There is no reason whatsoever to assume that the "code" read from the keyboard is ASCII. We don't know what it is, and the 8 bits that are read get mangled in surprising ways by the interface board which makes me all the more sure it isn't ascii. But this is by no means surprising. It would make sense to push the mapping of keyboard scan codes off to the host machine (Nova). On the other hand it absolutely does seem that data received from the host by the terminal is ascii.

A write to 0x70 yields a low going pulse on the signal "outp_70*" which originates in the processor board and goes to pin 29 on the edge connector. The backplane schematic shows that this goes to pin 30 on the interface board. We again call this signal "outp_70*" on the interface board schematic.

Along with driving outp_70* low, a write to port 0x70 also puts 8 bits of data out onto the output data bus (DO0 through DO7). Typically these data is latched into some chip via the outp_70* signal, but something more complex is going on here.

Oddly enough, the only place on the schematic where is see outp_70* is on pin 1 of UB7. This is an inverter and is part of some logic that generates the DN_CLOCK signal (which clocks the lower 8274). Frankly this makes little sense and I suspect that something is amiss here and/or there may be additional connection on UB7 -- but who knows. The floating input (pin 3) on UA7 is also suspicious (any floating input on TTL is suspicious).

Consider the Signetic 8274 chips

These are 10 bit parallel to serial shift registers, exactly the sort of thing you would expect to be used to send data to the host. Why should they be 10 bits instead of 8? Are 2 bits simply unused? And why are there two of them?

Ignoring these burning questions for now, lets just look at the serial out of these two chips. I call UA4 the "upper" 8274 and UA3 the "lower". This is simply because UA4 is above UA3 on the schematic and because it is handy to have some name for these things. The serial out from the lower 8274 does exactly what you would expect. It drives the CG_data_out signal which goes directly to the 75113 driver chip and to pins B/F on the CG connectors. The serial out from the upper 8274 is surprising. It is routed (by way of an LS51 AOI chip) to the D0 pin on the lower 8274.

What I have yet to figure out about this is the following. The ten "D" inputs on the 8274 are ignored, except when S0 and S1 are commanding "LOAD". Each 8274 is driven by its very own clock (but both presumably derived from the CG_clock signal in some way -- another topic to get to the bottom of).

Setting all that aside for the time being, it is interesting to look at the parallel inputs to these two 8274 chips. This used to be complex and confusing, but after sorting out some errors in the schematic it seems orderly and interesting. The data sheet labels the parallel inputs D1 to D10 (whereas we label the signal on the data bus DO0 to DO7, so watch out). Each 8274 gets the same DO0 to DO6 on the D8 to D2 inputs (yes the order changes also). There is odd tricky business involving DO7 on the D1 pin. Here are the signals referenced to the D1 to D10 names on the chip datasheet

D1 - special DO7 logic (see below)
D2 - D06
D3 - D05
D4 - D04
D5 - D03
D6 - D02
D7 - D01
D8 - D00
D9 - Ground on the lower 8274, special on the upper 8274
D10 -- to VCC on both chips

Pretty simple and organized, eh? Now let's talk about the special logic. There is an odd chip (the 74LS51) that has a special relationship with these two 8274 chips. The LS51 is an "AOI" chip (And-Or-Invert) and has two sections (hence two output signals). Each output is followed by a LS04 inverter, cancelling the output inversion, making the scheme just an "AO" (and-or). To make a long story short, what they are doing with this chip is using it as a dual 2 input multiplexor. The signal "LOAD" selects which of two inputs comes out of each section of the LS51. This used to seem odd and mysterious, now it is so very simple. Here is the game:

A special side note here. The 8274 datasheet says that "the D1 input may also be used for serial entry". Aha! This hints at why special logic has been set up to feed this input.

Upper LS51

    LOAD = 1, output is DO7
    LOAD = 0, output is Vcc

Lower LS51

    LOAD = 1, output is DO7
    LOAD = 0, output is serial data from upper 8274

The upper LS51 feeds the D1 input of the upper 8274.
The upper LS51 feeds the D1 input of the lower 8274.

This leaves us with just the special input to D9 to talk about. This comes from the Q output of UC7B (pin 9). this is a good old LS74 "D type flip flop".

So now let's talk about that flip flop. The D and clock inputs (pin 11 and 12) are shown as floating, but we don't believe that for a minute, so let's assume they are both pulled high (or at least that pin 11 (the clock) is pulled high, taking them out of the game. Then just the Set* and Reset* inputs to the flipflop matter. The "reset" gets pulled low when there is a write to port 0x78 with DO4 = 1 and DO7 = 0. The "set" gets pulled low when there is a write to port 0x78 with DO7 = 1. In other words software is in control of this flip flop.

The way this flip flop is used is very similar to how the pair of JK flip flops in UA5 are used. They are also controlled by software by bits in port 0x78, but in a slightly different way. I need to work up another entire page about the 8 bits in port 0x78 and what they do.

The LOAD* signal

This signal goes to both 8274 chips. Before we talk about it, let's talk about the S0 and S1 inputs to the 8274 chips. I call this pair of signals the "what the heck is going on" signals. As you might guess, with 2 binary inputs, there are 4 things that could possibly be going on. On the Entrex interface board, the S0 input is always pulled up (connected to Vcc), so we never see the two states (hold and clear) that might happen if it was zero. The LOAD* signal goes to the S1 input. When S0 is 0, we load the shift register from the parallel inputs. When S0 is 1, we shift data out the serial out pin.

So, you can see that LOAD* is active low as far as telling the 8274 to latch data from the parallel inputs. This signal also goes to many other parts of the circuit. Not only that, it is inverted (producing active high LOAD) and that right side up signal goes to other parts of the circuit. Of course you could view LOAD as an active low "SHIFT" and likewise you could view LOAD* as active high SHIFT. So pay attention and keep your head straight.

The surprise to me is that LOAD* is not derived in some simple way from the "outp_70*" signal. I mean we had better latch the data on the DO bus while it is valid, which is only when the "outp_70" signal is active.


The data sheet for the 8274 is a miserable thing. They give you a functional schematic of the insides of the chip and leave it to you to figure out what is going on.

One thing is clear. The first bit coming out of the chip as it shifts is D10. As data shifts out of D10, everything slides over and the input on D1 replaces what was previously in D1.

The question any sane person should be asking about the Entrex design, is "why two 8274 set up in series?" We have the same 8 bit word presented to the parallel input of each -- why do we want to transmit two copies of it?

Feedback? Questions? Drop me a line!

Tom's Computer Info /