April 28, 2023

Entrex - Flip flops and the interface board

My purpose here is to talk about the 74LS74 chips on the interface board.

First, lets talk about flip flops, since each LS74 chip has two of them (being a dual flip flop). A flip-flop is a single bit with a number of ways to examine and modify its state. It is as simple as that -- a one bit memory.

The LS74 is what is called a "D flip flop", we will get to the details of that in a minute. You also see another type, the "JK flip flop", but it is definitely less common. This is the LS107 chip and there are several on the processor board, we won't talk about those here. Let's talk about the 5 signals going in and out of one section of a LS74. It is all painfully simple -- once you understand it. Just remember that at the heart of it all is a single bit tucked away inside the flip flop.

D - input data
CP - input clock (probably a pulse)
R - input: active low reset
S - input: active low set
Q - output: the state of the bit
Q* - output: the state of the bit inverted
So there you go, 6 signals, 4 inputs and 2 outputs.

As for the outputs, they give you the internal bit in both normal and for convenience as inverted form. This saves you having to use an inverter if you need it upside down. Often the inverted output Q* is left unconnected, which is perfectly fine.

For inputs, consider first R and S. Pull R low and "bam!" the internal bit gets set to 0 (i.e. reset). Similarly for S, pull S low and "bam! the internal bit gets set to 1.

The other two inputs D and CP work together. It is like this. When CP transitions from high to low (a falling edge), whatever is on the D input gets copied to the internal bit.

And there you have it. All you need to know about a D flip flop. What is missing of course is examples of how this all might be used. I'll note before I move on that the R, S, and CP inputs should always be pulled up (or just driven) if not used, otherwise they are little antennas looking to pick up noise and do unpredictable things at unpredictable times.

A side note on reset

Many of the flip flops on the interface board have their reset inputs connected to a common signal that I decided to name "reset*" (it is active low). It is driven by an AND gate (acting as an active low OR gate). As it turns out the two inputs to this OR gate are a reset signal generated on the interface board by a circuit with two transistors and a diode (a power up reset circuit), or by a signal coming from P15-79 on the card edge. We trace the card edge circuit through the backplane to J17_80 from the processor board (as we might have suspected). The circuit that generates this reset is very interesting. It is part of what AJ dubbed the "what is all this nonsense?" section at the top of his schematic. Here we have another AND gate acting as an active low OR. The two conditions that generate a reset are either power on (from another circuit with a transistor) or a write to port 0x40! How about that, software can produce a reset (of the interface board anyway).

And hey! For you flip flop afficianados we have up here a pair of NAND gates connected into the classic RS flip flop circuit you always read about in textbooks. So, if you didn't know, you can build a flip flop from a pair of NAND gates -- now you know. Even more exciting, there is an arrangement to read the state of this RS flip flop via a read to input port 0x40.
Here is what the classic RS flip flop circuit looks like:

In our case a pair of 3 input NAND gates is being used, they just tie two inputs together to be able to use them as 2 input NAND gates.

It will be interesting to look at the ROM code to see when and why it writes to port 0x40 (note that it will be a write with no particular data, just writing to that port yields the reset). Equally interesting will be to see when and why it might read port 0x40.

Flip flops on the interface board

To my count there are 7 LS74 chips on the interface board. That gives us 14 fully independent flip flops. In other words we have 14 "state bits" doing who knows what. My thesis is that understanding what these 14 bits are, is the heart of the interface board. So I want to study them and if possible give them all names as I figure out their purpose. Wish me luck!

Here is my plan. I am going to scan the schematic starting at the upper left, scanning down, then when I get to the bottom, move a bit right and up top, then scan down again.


As drawn both R and S are floating (which is bad and seems unlikely). D is connected to ground and CP is driven by CG_inD (from the N/R pair). So a falling edge on CP clocks a 0 into the flip flop. I suspect an errata here and that something drives the "S" input at least. Only Q* is used.


R is driven by Reset* (makes sense). S is driven by u7_6. D is connected to ground, so a falling edge on CP will clock a zero into the flip-flop. The clock is from a 4 input NAND gate. Q* is unused, but Q drives our status register (so the state can be read by reading port 0x78 and in binary is bit 0000_0010). Q also drives some logic that will enable the 75113 chips for the data_out signals.
Feedback? Questions? Drop me a line!

Tom's Computer Info / tom@mmto.org