The 8x305 differs from the 8x300 in only a few ways. It allows a higher clock rate (it could run at 10 Mhz, though in the CWC it runs at only 6.667 Mhz, which could be handled by a 8x300. The 8x305 has additional registers:
r12 # 8x305 only, can't use for normal XMIT
r13 # 8x305 only, can't use for normal XMIT
r14 # 8x305 only
r15 # 8x305 only
r16 # 8x305 only
I am not at all convinced that the Callan code uses the extra registers.
Given the clock and the fact that the code doesn't use the extra registers,
it looks to me like they could use either an 8x300 or a 8x305 according to
what was available in the supply chain at the time (1982).
The data path has an ALU and a left shift unit on the output. I see right shift notations on and, add, xor, and move instructions. There is also a right shift/rotate on the input to the ALU. This is apparently what my disassembler is indicating.
The IV bus is interesting. It has a left and right side. You "xmit" a constant to ivl or ivr first. Then you use one of sliv, sriv, dliv, driv to access the value. "s" is for source (on the left side of a comma) and "d" is for destination (on the right side of a comma).
The "nzt" is a "test non zero and branch if so" instruction. Otherwise it just falls through.
The "xec" is my favorite. It executes an instruction off someplace else just once. If that instruction is a jmp, then you jump, but otherwise execution just falls through. This instruction is often used to set up jump tables. Something like "xec x0080,aux" will add the contents of aux to the base of the table (namely x0080) and execute that. Since each instruction is 1 word, there is not need to scale the value in aux as there would be for other processors.
Tom's Computer Info / tom@mmto.org